[CI] Fix integer widening (Spike v1.0.2) + regression test

.github/workflows/pytorchsim_test.yml

@@ -191,6 +191,25 @@ jobs:
             -e vpu_spad_size_kb_per_lane="${{ inputs.spad_size }}" \
             ${{ inputs.image_name }} python3 PyTorchSim/tests/ops/view/test_floormod_axis_split.py
 
+  test_widen_dtype:
+    name: Run test_widen_dtype.py
+    runs-on: ubuntu-latest
+    steps:
+      - name: Log in to GitHub Container Registry
+        uses: docker/login-action@v3
+        with:
+          registry: ghcr.io
+          username: ${{ github.actor }}
+          password: ${{ secrets.GITHUB_TOKEN }}
+
+      - name: Run test_widen_dtype.py
+        run: |
+          echo "Running test_widen_dtype.py"
+          docker run --rm \
+            -e vpu_num_lanes="${{ inputs.vector_lane }}" \
+            -e vpu_spad_size_kb_per_lane="${{ inputs.spad_size }}" \
+            ${{ inputs.image_name }} python3 PyTorchSim/tests/ops/misc/test_widen_dtype.py
+
   test_matmul:
     name: Run test_matmul.py
     runs-on: ubuntu-latest

tests/ops/misc/test_widen_dtype.py

@@ -0,0 +1,30 @@
+import os
+import sys
+import torch
+sys.path.insert(0, os.path.join(os.environ.get("TORCHSIM_DIR", default="/workspace/PyTorchSim"), "tests"))
+from _pytorchsim_utils import test_result
+
+
+def _widen(device, name, src_dtype, dst_dtype, lo, hi):
+    # Widening conversions lower to vsext.vf*/vzext.vf* (VI_VV_EXT). A Spike bug
+    # wrote every lane's result to lane 1 (vu_idx dropped), zeroing the rest; this
+    # guards against that regression. Signed / uint8<128 only, so the sign-extension
+    # is correct independent of the separate uint8->int8 dtype issue (#238).
+    a = torch.randint(lo, hi, (128, 128), dtype=src_dtype)
+    fn = lambda a: a.to(dst_dtype)
+    res = torch.compile(dynamic=False)(fn)(a.to(device=device))
+    out = fn(a)
+    test_result(name, res, out)
+
+
+def test_widen(device):
+    _widen(device, "int8->int16",    torch.int8,  torch.int16,  -128, 128)
+    _widen(device, "int8->int32",    torch.int8,  torch.int32,  -128, 128)
+    _widen(device, "int16->int32",   torch.int16, torch.int32, -1000, 1000)
+    _widen(device, "uint8->int32",   torch.uint8, torch.int32,     0, 128)
+    _widen(device, "uint8->float32", torch.uint8, torch.float32,   0, 128)
+
+
+if __name__ == "__main__":
+    device = torch.device("npu:0")
+    test_widen(device)

thirdparty/github-releases.json

@@ -13,7 +13,7 @@
   },
   "spike": {
     "repository": "PSAL-POSTECH/riscv-isa-sim",
-    "release_tag": "v1.0.1",
+    "release_tag": "v1.0.2",
     "asset_name": "spike-release.tar.gz"
   }
 }