[CI] Fix integer widening (Spike v1.0.2) + regression test#268
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Guards the Spike VI_VV_EXT (vsext/vzext) lane bug where widening int conversions (int8/int16 -> wider via tensor.to) returned scrambled/zero output. Signed and uint8<128 only so it is independent of the separate uint8->int8 dtype issue (#238). Requires the riscv-isa-sim fix (PSAL-POSTECH/riscv-isa-sim#4) in the pinned Spike; add to the CI allowlist + bump thirdparty/github-releases.json spike tag once that release is cut. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
v1.0.2 includes the riscv-isa-sim VI_VV_EXT fix (PSAL-POSTECH/riscv-isa-sim#4) so integer widening conversions no longer scramble. Bumping the pin changes the thirdparty base-image hash, so ensure-base rebuilds the base with the new Spike. Wire test_widen_dtype.py into the allowlist now that the fixed Spike is pinned. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Fixes integer widening dtype conversions (
int8/int16 -> widerviatensor.to), which were silently scrambled/zeroed.Root cause (Spike): widening lowers to
vsext.vf*/vzext.vf*(VI_VV_EXT). Spike wrote each result viaelt<T>(rd_num, i, true)-- the literaltruebound to thevu_idxparameter, so every lane's result went to lane 1 and the others stayed zero. Fixed in PSAL-POSTECH/riscv-isa-sim#4 (released as v1.0.2).This PR:
tests/ops/misc/test_widen_dtype.py-- regression test (int8/int16 + uint8<128 widening; signed/small-unsigned so it is independent of the separate uint8->int8 issue [Bug][Frontend] uint8 and bool dtypes silently downcast to int8 via MLIR_TO_DTYPE round-trip #238).thirdparty/github-releases.json. The base-image pin issha256(github-releases.json + Dockerfile.base), soensure-baserebuilds the base with the fixed Spike automatically.pytorchsim_test.yml).Verified locally with a Spike built from the v1.0.2 source: all widening cases go FAIL -> PASS (Spike+gem5 allclose).
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