Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.
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Updated
Jun 30, 2026 - Python
Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.
Modular AI/ML framework in MATLAB for classification tasks: my PhD project T-DTS v3 (2006-2009) of tree-based, entropy-driven, RBF and other enabled ANN tools, based on Dr. M. Rybnik's (my credits) initial v.1.0 T-DTS project
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