Portable HyperRAM controller

A Docker image for Mentor/Siemens Questa

Formal AXI verification properties from the eXpect framework for secure SoC validation

Utilities for Avalon Memory Map

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

✅ Formal verification of a 16-bit SIMD processor

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

Examples for 「Questa-Altera FPGA Starter Editionで始めるRTL検証」

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim

Configurable CRC-8/16 RTL with full UVM verification (SystemVerilog, QuestaSim). Serial and parallel modes.

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

Procesor ve VHDL pro jazyk Brainfuck

An application using Qeusta FPGA student version of Intel

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

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