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aarch64: call_indirect (§4.4.8 traps) + globals + param homing (#851) - #899

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aarch64: call_indirect (§4.4.8 traps) + globals + param homing (#851)#899
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@avrabe avrabe commented Jul 30, 2026

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v0.54 lane L3. Closes the two largest remaining STRUCTURAL declines on aarch64. Lane was interrupted by an API error mid-flight and resumed; all 9 commits pushed.

What lowers now

call_indirect — a synth-emitted .text-resident funcref table (__synth_func_table), one 8-byte [u32 structural-class-id][b func_N] record per slot across all tables, null slots [0][brk #0]. All three WASM §4.4.8 traps are emitted inline, because A64's blr is total and gives none for free (the #709 more-total-than-WASM class): out-of-range index (unsigned compare), null slot, signature mismatch.

The compared id is structural, not the raw type index — duplicate-but-identical types must stay interchangeable, and comparing type indices would trap where wasmtime calls. x16/x17 (AAPCS64 IP0/IP1) carry the slot address and class id, outside both the temp pool and the arg registers.

Globalsglobal.get/global.set for i32/i64; each global is an 8-byte slot in a synth-emitted .data region (__synth_globals) carrying its decoded constant initializer.

Param homing was the unlock. A non-leaf function referencing a parameter used to loud-decline — and a table index almost always is a parameter, so without this call_indirect could only dispatch on constants. Non-leaf functions now slot every local and store incoming arg registers at the prologue. Leaf functions are byte-identical, so writing a param still declines there and that ledger entry stays valid.

Globals base register — stated plainly

There is no globals base register, and no new precondition. synth emits both regions into the object and reaches them with adrp + add :lo12: that the linker resolves. x28 (linear-memory base) remains the one aarch64 precondition; the FEATURE_MATRIX row now says so in those words and lists the globals region and funcref table as explicitly NOT preconditions. Pinned as SYNTH-MATRIX-AARCH64-EMITTED-NOT-PRECONDITION, red-first verified.

PC-relative addressing also removes the #275/#717 base-register collision class by construction — there is no base register to collide with.

Trap evidence, including an oracle that was wrong

aarch64_call_indirect_851_differential.py: 35 checks, 23 traps, vs wasmtime under unicorn.

The first version of this oracle passed a compiler with the bounds guard removed. Past-the-end bytes read as class id 0, so the type check trapped anyway and masked the missing guard. The fixture now declares two tables, so index 4 of table 0 lands on table 1's fully valid, type-matching $mul slot — only the bounds guard can trap there, and a dropped per-table base offset returns 30-vs-13 instead of agreeing by coincidence. Five injected miscompiles now go red (weakened bounds guard, dropped base offset, removed type check, callable null slot, dense globals layout).

One is not decidable by execution: a signed bounds compare traps under emulation via an unmapped fault but is unsound on silicon. Pinned instead by a word-for-word guard-sequence unit test (verified red, exit 101).

Still declining, with machine reasons

Imported global · global with no decoded const initializer (float/v128/non-const) · v128 global · growable imported table · unverifiable element segment · table slot holding an imported function · non-leaf float param · anything past the 12-bit guard immediates.

All seven are in the CI-wired decline oracle, which asserts the reason substring, not merely that compilation failed. The load-bearing one: an unverifiable element segment declines rather than shipping the all-null table the existing reconstruction produces — that would trap on every dispatch, i.e. conservative-looking but wrong in the other direction.

Numbers

gale's acceptance matrix 45 ops / 119 native checks, empty declined frontier (was 32). aarch64_selector_ops 161 → 164. Parity-gate ledger entries for globals deleted and call_indirect flipped to Ok(()) in the same commit as the lowering.

Both oracles carry # ci-status: wired; CI steps use set -euo pipefail + count grep + RESULT: PASS, mutation-proven.

Coordinator: re-run --emit-status once after fan-in (L2 moves the same counter). Expect conflicts in cross_backend_op_parity.rs (aarch64_lowers signature + new a64_module_ctx()) and CHANGELOG.md.

Advances #851.

avrabe and others added 9 commits July 30, 2026 14:35
Adds the five A64 primitives lane L3 needs, each pinned to
`clang -c -target aarch64-linux-gnu` ground truth in a unit test:

  blr xn              — the indirect-call branch (call_indirect dispatch)
  adrp xd, <sym>      — PC-relative page address (the data-region reach)
  cmp wn/xn, #imm12   — flags-only immediate compare (no scratch register)
  add xd,xn,wm,uxtw#s — scaled zero-extended index add (table slot address)

`adrp`'s 21-bit page delta splits across TWO disjoint fields (immlo[30:29] +
immhi[23:5]); a contiguous placement is silently wrong for every delta >= 1,
so the split is pinned by a second test against capstone decodes of the
literal words (0xF0000000 = adrp x0,#0x3000; 0x90000020 = #0x4000;
0xF0FFFFE0 = #-0x1000).

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
The substrate both lane-L3 features need, with NO new precondition.

`DataBlob` — a synth-EMITTED `.data` (PROGBITS, ALLOC|WRITE, align 8) plus
`STT_OBJECT` symbols into it. This is the honest answer to "where do WASM
globals live on a backend that emits no startup and no linker script": the
bytes ARE the initial values, shipped in the object; the linker places the
section; code reaches it with `adrp`+`add :lo12:`. Contrast `x28` (the
linear-memory base), which IS an embedder precondition — globals add no
second one.

RelocKind gains the three AArch64 kinds beyond CALL26: JUMP26 (282, the
funcref-table `b func_N` trampolines), ADR_PREL_PG_HI21 (275) and
ADD_ABS_LO12_NC (277) (the symbol-address pair). The builder's kind→type
mapping has NO wildcard, and an unplaceable symbol now PANICS instead of
silently dropping the relocation — an unrelocated `adrp #0` would address the
wrong page (silent miscompile), where the old `continue` merely assumed it
could not happen.

`ElfFunction::is_object` types the `.text`-resident funcref table as OBJECT,
not FUNC: it is branched INTO at slot+4, never called at slot+0.

Byte-identity: an empty `DataBlob` reproduces the previous 5-section layout
exactly (asserted by `empty_data_blob_is_byte_identical_to_the_data_free_builder`),
so every globals-free module is unchanged.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
…dispatch (#851)

Three additions the aarch64 `call_indirect` + globals lowerings consume:

* `DecodedModule::structural_type_class_ids()` — factored out of
  `call_indirect_guards`, which exposed the ids ONLY when its heterogeneous-
  table sidecar existed. The aarch64 dispatch type-checks UNCONDITIONALLY, so
  it needs them always. These are STRUCTURAL classes, not raw type indices:
  WASM type equality is structural, so `call_indirect (type 1)` must reach a
  function declared with a duplicate `type 0` (SS4.4.8) — comparing indices
  would trap where wasmtime calls.
* `DecodedModule::funcref_region_class_ids()` — per-slot class id in the same
  contiguous order as `funcref_region_slots()`, 0 for null/unclassifiable.
  Storing this beside each slot makes ONE compare serve as both the SS4.4.8
  type check and the null check (0 never equals a real class, which is >= 1).
* `type_result_counts` on `DecodedModule` + `CompileConfig` — an indirect
  callee is known only by its static type, and `type_ret_i64/f32/f64` conflate
  void with i32, so the 0-vs-1 "is a value pushed back" distinction needs its
  own table.

Plus `CompileConfig::a64_substrate_emitted`, FAIL-SAFE at `false`: the aarch64
selector will loud-decline globals and `call_indirect` unless the driver has
actually emitted the `.data` globals image and the `.text` funcref table, so a
driver that compiles bodies without emitting the regions cannot ship code
addressing a symbol that is not there.

Behavior unchanged: `call_indirect_guards` output is identical (pure
refactor), and no consumer reads the new fields yet.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
…851)

`substrate::plan` materializes the globals `.data` image and the `.text`
funcref table from decoded module state, and is called by BOTH aarch64 ELF
drivers, so the regions the code addresses and the regions the object ships
cannot disagree.

PRECONDITION STATUS, stated plainly: neither region is one. Both are EMITTED
BY SYNTH and reached with `adrp` + `add :lo12:` against a symbol the same
object defines. That is deliberately unlike `x28` (the linear-memory base),
which IS an embedder precondition — v0.53 made that explicit so the next
feature would not quietly add a second, and this one does not. Using
PC-relative addressing instead of a dedicated base register also sidesteps the
#275/#717 collision class outright: there is no base register to collide with.

Layouts. Globals: ONE 8-BYTE SLOT PER GLOBAL at `k*8` (NOT the ARM/#643 dense
width-summed layout) — uniform slots stay naturally aligned for `ldr x`, where
a dense layout puts an i64 at offset 4, and the offset stays a foldable
constant. Funcref table: 8 bytes per slot, `[u32 structural class id][b
func_N]`, null slots `[0][brk #0]`.

Every unrepresentable shape LOUD-DECLINES with a machine reason rather than
guessing (9 unit tests, decline text asserted): imported globals (value
arrives at instantiation), a global with no decoded const initializer
(float/v128/non-const expr), >2048 globals or a v128 slot, an unsized
(growable imported) table, >4095 slots or class ids past the 12-bit guard
immediates, and a table slot holding an imported function.

The load-bearing one: an UNVERIFIABLE element segment declines instead of
shipping a table. `funcref_region_slots` degrades such a table to all-null,
which traps on every dispatch — that LOOKS conservative but is wrong in the
other direction, trapping where wasmtime calls successfully.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
Three parity-gate entries flip Err(reason) -> lowering in this commit, so no
gap claim outlives its gap: `global.get`, `global.set` (ledger entries deleted)
and `call_indirect` (`a64_extended_surface` -> `Ok(())`).

GLOBALS. `global k` lives at `__synth_globals + k*8` in the `.data` image synth
EMITS; the address is formed `adrp`+`add :lo12:`. i32/f32 use the low word of
the slot, i64/f64 the whole slot, and the size-scaled load/store immediate
folds the offset. PRECONDITION STATUS: none. Unlike `x28` (the linear-memory
base, which IS an embedder precondition), synth ships the region and its
initial values; the linker places it. No base register, so nothing can collide
with the linear-memory base the way #275/#717 did on ARM.

CALL_INDIRECT. All three §4.4.8 traps are emitted, none inherited from `blr`:

  cmp w_idx,#size / b.lo +2 / brk      out-of-range index
  adrp+add / add x16,x16,w_idx,uxtw#3  slot address (no base register)
  ldr w17,[x16] / cmp w17,#expected    signature mismatch — and, because a
  b.eq +2 / brk                        null slot's class id is 0 and every
                                       real class is >=1, the null check too
  add x16,x16,#4 / blr x16             the slot's tail-branch trampoline

The compared id is STRUCTURAL, so duplicate-but-identical types stay
interchangeable; comparing raw type indices would trap where wasmtime calls.
x16/x17 are the AAPCS64 IP0/IP1 scratch registers — outside both the value-
stack temp pool (x9..x15) and the argument registers, so no guard can alias a
live value.

PARAM HOMING was the blocker: a non-leaf function referencing a parameter
loud-declined, and a table index almost always IS a parameter, so
`call_indirect` would only have dispatched on constants. Non-leaf functions now
give EVERY local (params included) an 8-byte stack slot and store the incoming
argument registers there at the prologue, reusing the non-param-local machinery
verbatim. That restores both properties the decline protected: a post-call read
hits the slot (which the call cannot clobber), and every value-stack entry is a
temp again, so argument marshalling stays hazard-free. LEAF functions are
untouched and byte-identical, so writing a param still declines there and that
ledger entry stays valid; a non-leaf FLOAT param also still declines (homing a
v-register needs an FP store this encoder lacks).

Verified end-to-end, not just in unit tests: both features compile, LINK with
a real `ld.lld`, and disassemble correctly — the linker relaxes `adrp`+`add`
to `adr`, resolves `__synth_globals` to the emitted `.data` (0x29 = 41,
0x11f71fb04cb = 1234567890123), and the table lays out as
`[1][b func_0] [1][b func_1] [2][b func_2] [0][brk #0]`.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
Two unicorn-vs-wasmtime differentials, both wired into the `aarch64-oracle`
job in this commit with `set -o pipefail` and a non-zero-count grep (the #890
"oracle exists and runs nowhere" class).

`aarch64_globals_851_differential.py` — 17 checks, 6 exports. Reads the INITIAL
values before anything is written (a region shipping zeros fails), then runs
the cases IN SEQUENCE against ONE region so a dropped or misdirected
`global.set` shows up in the next `global.get`. i32 and i64 globals are
interleaved, so a wrong slot stride shifts every later global.

`aarch64_call_indirect_851_differential.py` — 35 checks (23 trap, 12 value),
6 exports. All three §4.4.8 traps, plus the direction an "always trap" lowering
would hide: a structurally-DUPLICATE type must NOT trap.

Both harnesses act as the LINKER — they place `.text` and `.data` on different
pages and resolve ADRP page / ADD lo12 / JUMP26 themselves — so a wrong page
delta, lo12, or trampoline displacement diverges rather than passing.

RED-FIRST, and it earned its keep: the first version of the call_indirect
oracle PASSED a compiler with the bounds guard removed. Past-the-end bytes
read as class id 0, so the TYPE check trapped anyway and masked it. The fixture
now declares TWO tables, making index 4 of table 0 land on table 1's fully
valid, type-matching `$mul` slot — so only the bounds guard can trap there, and
the same fixture makes a dropped per-table base offset return 30-vs-13 instead
of agreeing by coincidence. Five injected miscompiles are now caught:

  weakened bounds guard    -> differential red (4 BUG lines)
  dropped base offset      -> differential red (2 BUG lines)
  removed type check       -> differential red (6 BUG lines)
  null slot made callable  -> differential red (2 BUG lines)
  dense globals layout     -> differential red (4 BUG lines)

One injection is NOT decidable by execution: a SIGNED bounds compare (`b.lt`
for `b.lo`). Under emulation a negative index passes the signed guard and then
faults on the unmapped scaled address, so it traps either way — but on real
silicon that address can be mapped and the dispatch would branch into it. It is
pinned instead by `call_indirect_guard_sequence_uses_an_unsigned_bounds_compare`,
which asserts the whole guard sequence word-for-word (verified red: exit 101
when only the shipped code, not the expectation, is mutated).

Plus fail-safe and scaling unit tests: both features decline under a default
`ModuleCtx`, the slot offset is size-scaled per access width, and a global
index past the region declines.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
)

The FEATURE_MATRIX template row now says plainly what v0.52's cold review
caught the last version of this doc getting wrong: the globals region and the
funcref table are EMITTED BY SYNTH, not preconditions. `x28` (the linear-memory
base) remains the ONE aarch64 precondition, and the row says so in those words,
so a reader cannot come away thinking lane L3 added a second ambient input.

The row also enumerates the new LOUD DECLINES by name rather than implying full
coverage: imported globals, a global with no decoded const initializer, a
non-leaf float param, a growable imported table, an unverifiable element
segment, and a table slot holding an imported function.

Two new `claims.yaml` pins hold those claims to evidence, both verified
RED-FIRST:

  SYNTH-MATRIX-AARCH64-EMITTED-NOT-PRECONDITION — flipping the sentence to
    "are ALSO preconditions" reddens the gate; pinned to substrate.rs, the
    `.data` DataBlob, and the ADRP relocation kind actually being emitted.
  SYNTH-MATRIX-AARCH64-CALL-INDIRECT-TRAPS — unwiring either oracle from
    ci.yml reddens the gate, so the §4.4.8 trap claim cannot outlive its
    execution evidence.

`aarch64_selector_ops` 161 -> 164 (global.get, global.set, call_indirect).
Generated status files regenerated with the script (NOT hand-edited); the
coordinator should re-run `--emit-status` once after the lane fan-in, since
every aarch64 lane moves this counter.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
… failing (#851)

Extends the CI-wired decline-matrix honesty oracle with the seven shapes lane
L3 deliberately refuses, and upgrades the oracle itself: an entry may now pin
the machine REASON its diagnostic must contain, because "it failed somehow" is
not evidence that it failed for the right cause — a decline with the wrong
reason is a different bug than a decline.

  imported global                      -> "imports 1 global"
  float global (no decoded const init) -> "no decoded constant initializer"
  v128 global                          -> (declines upstream at decode)
  growable imported table              -> "no compile-time size"
  passive element segment              -> "not statically verifiable"
  table slot holding an import         -> "imported function"
  non-leaf FLOAT param                 -> "FLOAT parameter"

10/10 loud-decline, 6 with their reason asserted; the oracle also fails if NO
entry carries a reason, so the new check cannot rot into a no-op.

Also verified across the whole aarch64 gate set: all 14 unicorn oracles exit 0,
`aarch64_calls_851.py` is 5/5 bit-identical, the `--relocatable` path emits the
funcref table too, and gale's native acceptance matrix now reports 45 ops
accepted / 119 native checks with an EMPTY declined frontier (baseline 32).

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
…, #851)

Two corrections from lane L1's oracle-wiring gate, applied to this lane's
harnesses.

1. Both new oracles carry `# ci-status: wired`. VERIFIED non-inert: pointing
   the workflow step at a different filename makes the gate report
   "declares `wired` but NO workflow STEP runs it — the gate is INERT",
   so the declaration is checked against the parsed executable surface rather
   than taken on trust.

2. The CI steps now use `set -euo pipefail`, not bare `set -o pipefail`.
   `pipefail` alone leaves the step's exit status as its LAST command's, so a
   harness that printed FAIL and exited 1 could still green the step — the
   precise #890 class. The verdict is now taken three ways: the script's own
   exit status (via `-e`), a non-zero check-count grep, and the summary
   `RESULT: PASS` line.

MUTATION-PROVEN, not assumed: perturbing the comparison inside the
call_indirect harness (`exp` -> `exp + 1`, so a CORRECT compiler mismatches)
makes the exact CI step body exit 1, and restoring it returns exit 0. That is
the check L1 found `sret_decide_differential.py` failing — a gate that printed
`MISMATCH <-- BUG` and exited 0.

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L
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Automated review for PR #899

pulseengine/synth:l3-aarch64-indirect-globals → pulseengine/synth:main

Verdict: 💬 Comment

Summary: The code has been modified to include new features and changes that need to be reviewed.

Findings: 0 mechanical (rivet) · 1 from local AI model.

Findings (1):

  1. scripts/repro/aarch64_globals_851.wat:2
    ;; #851 lane L3 — aarch64 globals execution differential fixture.
    
    The code has been modified to include new features and changes that need to be reviewed.

Generated by a local AI model and post-validated against a strict JSON contract. Each finding includes the verbatim line being criticised — verify by reading the file at the cited location.

Reviewed at 5dbd791

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codecov Bot commented Jul 30, 2026

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