[AMD] Minimax-M3-MXFP8 Eagle3 Draft attention backend override TRITON_ATTN for performance/Minimax-M3-MXFP8 Eagle3草稿模型的注意力后端固定为 TRITON_ATTN以提高性能#2107
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…for perf Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
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Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
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Claude finished @hongxiayang's task in 1m 49s —— View job PR ReviewLGTM - no blocking issues found Verified:
Non-blocking observation: the sibling AMD recipes |
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LGTM — small, self-contained recipe tweak adding an explicit attention_backend override for the EAGLE3 drafter, plus matching comment and changelog entry.
Extended reasoning...
Overview
This PR makes a single functional change to benchmarks/single_node/fixed_seq_len/minimaxm3_fp8_mi355x_mtp.sh: it adds "attention_backend": "TRITON_ATTN" to the JSON passed to --speculative-config, pinning the EAGLE3 drafter's attention backend rather than letting it fall back to a slow default. It also refreshes the recipe header comment to describe the new override and adds a corresponding entry to perf-changelog.yaml.
Security risks
None. This is a benchmark recipe script and a YAML changelog entry. No auth, crypto, permissions, or externally-exposed surface is touched. The change adds one string field to a JSON blob that's already interpolated into a CLI flag on the same line.
Level of scrutiny
Low. The recipe files under benchmarks/single_node/ are per-model launch scripts, not production inference code, and this PR touches exactly one line of vLLM CLI configuration on that recipe plus a matching changelog line. The full-sweep-fail-fast label is applied, so the change is being validated end-to-end by the benchmark sweep before merge. Follows the same pattern the CUDA EAGLE3 recipes already use for overriding the drafter's attention backend.
Other factors
The bug hunter surfaced only two nits: grammar wording in the perf-changelog entry / recipe comment ("falls to" vs "falls back to", missing subject in the parenthetical) and missing Chinese translations in the PR title/body per AGENTS.md. Neither affects correctness — they can be addressed in a quick follow-up edit or left as-is at author discretion. No prior human reviewer comments are outstanding.
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28829536843 |
hongxiayang
changed the title
Signed-off-by: Hongxia Yang <hongxia.yang@amd.com>
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CC @seungrokj @chunfangamd as Codeowners to further review and signoff |
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/reuse-sweep-run |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28834955707 |
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As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this.
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this.
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
- If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
- If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
Additional detail section:
- insert any additional info here
m3 vllm recipe:
https://github.com/vllm-project/recipes/blob/main/models/MiniMaxAI/MiniMax-M3.yaml
Signed: seungrokj
❌❌❌ REJECTED ❌❌❌@seungrokj — the sign-off comment (id 4902845254) no longer exists on this PR (API returns 404 and no sign-off from you appears in the conversation or reviews), so the checklist and its additional-detail section cannot be verified. Please re-post the completed latest PR_REVIEW_CHECKLIST.md including the recipe link — everything else about this PR is to standard. ✅ Check 0 (CODEOWNER): PASS — @seungrokj is a recognized CODEOWNER ( |
seungrokj
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seungrokj
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There was a problem hiding this comment.
As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this.
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this.
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
- If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
- If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
Additional detail section:
- insert any additional info here
m3 vllm recipe:
https://github.com/vllm-project/recipes/blob/main/models/MiniMaxAI/MiniMax-M3.yaml
Signed: seungrokj
✅✅✅ Verdict: PASS ✅✅✅Supersedes the earlier REJECTED verdict for this SHA — the sign-off is now on record as a review with the recipe link, resolving Checks 3 and 5. ✅ Check 0 (CODEOWNER): PASS — @seungrokj is a recognized CODEOWNER ( |
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@functionstackx @Oseltamivir can you plz merge this ? |
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[AMD] Minimax-M3-MXFP8 Eagle3 Draft attention backend override TRITON_ATTN for performance
Tested on local 1k/1k and 8k/1k vs no override. the perf improves across all concurrencies.
在推测配置中将 EAGLE3 草稿模型的注意力后端固定为 TRITON_ATTN，避免回退到较慢的默认后端。在 MI355X TP4 MXFP8 上，1k/1k 和 8k/1k 各并发下吞吐均有提升
Associated vLLM recipe PR: vllm-project/recipes#615