From 5ff1441ff8e0ce760a98979d4c42ffb5a8a09cd2 Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 15:30:03 +0200 Subject: [PATCH 01/22] [IP] Fixed heap bufer overflow and stack overflows, main problem was with bad codegen ignoring if (a > b) conditions --- ir/licm.c | 7 +++++-- ir/opt/ssa_opt_branch.c | 4 +++- ir/opt_constprop.c | 18 +++++++++++++++--- ir/opt_utils.c | 10 ++++++++++ tccgen.c | 21 ++++++++++++++++++++- 5 files changed, 53 insertions(+), 7 deletions(-) diff --git a/ir/licm.c b/ir/licm.c index d1210730..8ee01bd2 100644 --- a/ir/licm.c +++ b/ir/licm.c @@ -177,8 +177,11 @@ IRLoops *tcc_ir_detect_loops(TCCIRState *ir) IROperand dest = tcc_ir_op_get_dest(ir, q); int target = (int)irop_get_imm64_ex(ir, dest); - /* Check if this is a backward jump (loop back edge) */ - if (target < i) + /* Check if this is a backward jump (loop back edge). The target must be + * a valid non-negative instruction index: an unresolved/sentinel dest can + * decode negative, which would make the loop body range [target, i] index + * before compact_instructions. */ + if (target >= 0 && target < i) { /* Found a loop */ if (loops->num_loops >= loops->capacity) diff --git a/ir/opt/ssa_opt_branch.c b/ir/opt/ssa_opt_branch.c index 5e49fb5a..8ae3c9b0 100644 --- a/ir/opt/ssa_opt_branch.c +++ b/ir/opt/ssa_opt_branch.c @@ -105,7 +105,9 @@ void ssa_drop_phi_edge(IRSSAOptCtx *ctx, int dead_pred_block, static int ssa_block_for_instr(IRCFG *cfg, int instr_idx) { if (!cfg || !cfg->instr_to_block) return -1; - if (instr_idx < 0) return -1; + /* instr_to_block is sized to num_instrs at CFG-build time; instructions + * appended by later passes index past it, so bound-check both ends. */ + if (instr_idx < 0 || instr_idx >= cfg->num_instrs) return -1; return cfg->instr_to_block[instr_idx]; } diff --git a/ir/opt_constprop.c b/ir/opt_constprop.c index dea399e7..49c44598 100644 --- a/ir/opt_constprop.c +++ b/ir/opt_constprop.c @@ -6330,7 +6330,12 @@ int tcc_ir_opt_cmp_expr_fold(TCCIRState *ir) int32_t bvr1 = irop_get_vreg(base1); int32_t bvr2 = irop_get_vreg(base2); - if (bvr1 >= 0 && bvr2 >= 0) + /* A dereferenced base `*(V)` (is_lval) and a plain address base `V` + * are different values even when V resolves to the same definition. + * Without this, `*(p) + K` (loaded value + K) is equated with + * `p + K` (an address), mis-folding `(c->field0 + K) > c->fieldK` + * (K == field offset) to a constant. */ + if (base1.is_lval == base2.is_lval && bvr1 >= 0 && bvr2 >= 0) { /* Same base vreg → equal */ if (bvr1 == bvr2) @@ -6577,11 +6582,18 @@ int tcc_ir_opt_cmp_const_offset_fold(TCCIRState *ir) IROperand ds1 = tcc_ir_op_get_src1(ir, dq); IROperand ds2 = tcc_ir_op_get_src2(ir, dq); + /* The CMP operand standing in for `b`. The ADD base must match it in + * lval-ness too: `*(V)` (loaded value) and `V` (address) share a vreg + * but are different values, so `a = *(V) + K` does not make `a == V + K` + * provable from `b == V`. */ + IROperand b_op = swap ? src1 : src2; + /* Match `a = b + K` (or `a = K + b`, commutative ADD). */ int64_t k = 0; - if (irop_get_vreg(ds1) == b && irop_is_immediate(ds2)) + if (irop_get_vreg(ds1) == b && ds1.is_lval == b_op.is_lval && irop_is_immediate(ds2)) k = irop_get_imm64_ex(ir, ds2); - else if (dq->op == TCCIR_OP_ADD && irop_get_vreg(ds2) == b && irop_is_immediate(ds1)) + else if (dq->op == TCCIR_OP_ADD && irop_get_vreg(ds2) == b && ds2.is_lval == b_op.is_lval && + irop_is_immediate(ds1)) k = irop_get_imm64_ex(ir, ds1); else continue; diff --git a/ir/opt_utils.c b/ir/opt_utils.c index dea8d07e..937248fa 100644 --- a/ir/opt_utils.c +++ b/ir/opt_utils.c @@ -985,6 +985,16 @@ static int ir_opt_pure_expr_equal_impl(TCCIRState *ir, IROperand a, int a_use_id if (a_tag != IROP_TAG_VREG || b_tag != IROP_TAG_VREG) return ir_opt_nonvreg_expr_equal(ir, a, b); + /* A dereferenced operand `*(V)` (is_lval) and a plain address operand `V` + * (not is_lval) are different values — one loads from memory, the other is + * the address itself — even when V resolves to the same definition. Without + * this guard, `c->field0 + K` (value-of-load + K) is treated as equal to + * `&c->field0 + K` (== &c->fieldK, an address), which mis-folds comparisons + * like `(c->size + K) > c->size_allocated` to a constant when K is the + * byte offset between the two fields. */ + if (a.is_lval != b.is_lval) + return 0; + a_vr = irop_get_vreg(a); b_vr = irop_get_vreg(b); if (a_vr < 0 || b_vr < 0) diff --git a/tccgen.c b/tccgen.c index e5bca23e..281359d7 100644 --- a/tccgen.c +++ b/tccgen.c @@ -27042,6 +27042,7 @@ static void decl_initializer(init_params *p, CType *type, unsigned long c, int f tcc_error("unhandled string literal merging"); while (tok == TOK_STR || tok == TOK_LSTR) { + int tok_width = (tok == TOK_STR) ? 1 : (int)sizeof(nwchar_t); if (initstr.size) initstr.size -= size1; if (tok == TOK_STR) @@ -27049,7 +27050,25 @@ static void decl_initializer(init_params *p, CType *type, unsigned long c, int f else len += tokc.str.size / sizeof(nwchar_t); len--; - cstr_cat(&initstr, tokc.str.data, tokc.str.size); + if (tok_width == size1) + { + cstr_cat(&initstr, tokc.str.data, tokc.str.size); + } + else if (size1 == (int)sizeof(nwchar_t) && tok == TOK_STR) + { + /* Mixing a narrow piece into a wide initializer (C permits e.g. + * `L"a" "b"`): widen each byte to an nwchar_t element instead of + * byte-copying it, which would otherwise be read back at the wider + * element stride below and over-read initstr. */ + const unsigned char *np = (const unsigned char *)tokc.str.data; + for (int z = 0; z < tokc.str.size; z++) + cstr_wccat(&initstr, np[z]); + } + else + { + /* A wide piece in a narrow (char) array is not representable. */ + tcc_error("unhandled string literal merging"); + } next(); } if (tok != ')' && tok != '}' && tok != ',' && tok != ';' && tok != TOK_EOF) From 05585e3fe0aa7f31d3263d616f2efcf7b300c6b5 Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 15:40:09 +0200 Subject: [PATCH 02/22] submodule fix --- tests/gcctestsuite/download_gcc_tests.sh | 64 +++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/tests/gcctestsuite/download_gcc_tests.sh b/tests/gcctestsuite/download_gcc_tests.sh index 1512862c..a4826f11 100755 --- a/tests/gcctestsuite/download_gcc_tests.sh +++ b/tests/gcctestsuite/download_gcc_tests.sh @@ -30,10 +30,68 @@ count_tests() { echo " compile: $(ls "$TORTURE_DIR"/compile/*.c 2>/dev/null | wc -l) execute: $(ls "$TORTURE_DIR"/execute/*.c 2>/dev/null | wc -l)" } -# Already present (full or sparse checkout)? Nothing to do. +# A handful of torture tests #include a file from a *sibling* testsuite +# directory, e.g. execute/pr30314.c does +# #include "../../gcc.dg/tree-ssa/pr30314.c" +# Those files live OUTSIDE the gcc.c-torture sparse path, so a sparse checkout +# omits them and the compile fails with "include file '...' not found" (the test +# harness uploads such includes to the device too, but only if they exist on +# disk). Scan the checked-out tests for "../"-escaping quoted includes, resolve +# each to a path inside this submodule, and sparse-add exactly those files. Loop +# a few times so an included file that itself pulls in another out-of-tree file +# is covered as well. +# +# No-op on a full checkout (every file is already present); guarded on the +# sparse-checkout config so we never slow-scan a full gcc working tree. +fetch_extra_includes() { + [ "$(git -C "$SUBMODULE_PATH" config --get core.sparseCheckout 2>/dev/null)" = "true" ] || return 0 + local scan_dir="$SUBMODULE_PATH/gcc/testsuite" + [ -d "$scan_dir" ] || return 0 + + local pass + for pass in 1 2 3; do + local -a missing=() + local line file inc abs rel + # grep -H prints "FILE:#include "...""; split on the ":#" before the + # directive to recover the including file, then pull the quoted path. + while IFS= read -r line; do + file="${line%%:#*}" + inc="$(printf '%s\n' "$line" | sed -E 's/.*"([^"]+)".*/\1/')" + [ -n "$file" ] && [ -n "$inc" ] || continue + abs="$(realpath -m "$(dirname "$file")/$inc" 2>/dev/null)" || continue + case "$abs" in + "$SUBMODULE_PATH"/*) rel="${abs#"$SUBMODULE_PATH/"}" ;; + *) continue ;; # include escapes the submodule entirely; skip + esac + [ -f "$SUBMODULE_PATH/$rel" ] || missing+=("$rel") + done < <(grep -rHoE --include='*.c' \ + '#[[:space:]]*include[[:space:]]*"\.\.[^"]*"' "$scan_dir" 2>/dev/null) + + [ "${#missing[@]}" -eq 0 ] && return 0 + + local -a uniq=() + local m + while IFS= read -r m; do + [ -n "$m" ] && uniq+=("/$m") # leading "/" anchors the no-cone pattern at repo root + done < <(printf '%s\n' "${missing[@]}" | sort -u) + + echo " fetching ${#uniq[@]} out-of-tree include file(s) referenced by torture tests" + # The repo is already in no-cone mode (set during sparse_fetch), so `add` + # inherits it; a partial clone lazily fetches the newly in-scope blobs. + git -C "$SUBMODULE_PATH" sparse-checkout add "${uniq[@]}" || { + echo "warning: could not sparse-add include files: ${uniq[*]}" >&2 + return 0 + } + done +} + +# Already present (full or sparse checkout)? Nothing to fetch — but still make +# sure the out-of-tree include files are there (a sparse checkout from before +# this script learned to fetch them would be missing them). if [ -d "$TORTURE_DIR/compile" ] && [ -d "$TORTURE_DIR/execute" ]; then echo "GCC torture tests already available:" echo " $TORTURE_DIR" + fetch_extra_includes count_tests exit 0 fi @@ -78,6 +136,10 @@ else git -C "$SUPER_DIR" submodule update --init --depth 1 "$SUBMODULE_REL" fi +# Fetch the few out-of-tree files torture tests #include (gcc.dg/, gcc.target/) +# while the gitdir is still standalone and the just-fetched objects are local. +fetch_extra_includes + # Normalize the gitdir into the superproject's .git/modules layout so that # `git submodule status` and future submodule commands treat it like any other # submodule (best-effort; a standalone .git also works fine for the tests). From 5ef1004bbddcf5281a21210bad98b1d48da3583d Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 16:47:52 +0200 Subject: [PATCH 03/22] gcc-torture: always fetch the pinned commit, never gcc master The sparse downloader fell back to fetching the remote's default branch (origin HEAD = current gcc master) whenever the partial+sparse fetch of the pinned SHA didn't take. On CI that silently tested an ever-advancing gcc and failed on brand-new upstream tests that didn't exist when the submodule was pinned. Always end at the pinned commit instead: - drop the default-branch fallback; error out if the pin can't be resolved - add full_fetch(): a non-sparse but still *pinned* fetch that talks to the remote directly, so it works even though the submodule has `update = none` (which makes `git submodule update` skip it) Also fetch the handful of out-of-tree files the torture tests #include (gcc.dg/, gcc.target/) which the gcc.c-torture sparse path omits, so the on-device/QEMU compile no longer fails with "include file not found". Co-Authored-By: Claude Opus 4.8 (1M context) --- tests/gcctestsuite/download_gcc_tests.sh | 42 ++++++++++++++++++++---- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/tests/gcctestsuite/download_gcc_tests.sh b/tests/gcctestsuite/download_gcc_tests.sh index a4826f11..10b848e4 100755 --- a/tests/gcctestsuite/download_gcc_tests.sh +++ b/tests/gcctestsuite/download_gcc_tests.sh @@ -125,15 +125,45 @@ sparse_fetch() { git -C "$SUBMODULE_PATH" checkout -q FETCH_HEAD || return 1 } +# A non-sparse but still *pinned* fetch into the submodule path: fetch only the +# pinned commit (all blobs, depth 1) and check it out. Used as the fallback when +# the fast partial+sparse fetch doesn't work. It talks to the remote directly +# rather than going through `git submodule update`, so it is unaffected by the +# submodule's `update = none` setting in .gitmodules (which makes the recursive +# checkout — and `submodule update` — skip this submodule entirely). +full_fetch() { + local committish="$1" + [ -n "$committish" ] || return 1 + rm -rf "${SUBMODULE_PATH:?}/.git" + mkdir -p "$SUBMODULE_PATH" + git -C "$SUBMODULE_PATH" init -q || return 1 + git -C "$SUBMODULE_PATH" remote add origin "$URL" 2>/dev/null \ + || git -C "$SUBMODULE_PATH" remote set-url origin "$URL" || return 1 + git -C "$SUBMODULE_PATH" fetch --depth 1 origin "$committish" || return 1 + git -C "$SUBMODULE_PATH" checkout -q FETCH_HEAD || return 1 +} + echo "Fetching torture tests (sparse + partial)..." -if sparse_fetch "$PIN"; then +if [ -z "$PIN" ]; then + # IMPORTANT: never fetch the remote's default branch as a fallback. Doing so + # would silently pull the *current gcc master tip* instead of the pinned + # commit, so CI would test against an ever-advancing gcc and fail on + # brand-new upstream tests that didn't exist when the submodule was pinned. + echo "error: could not resolve the pinned gcc-testsuite commit; refusing to" >&2 + echo " fetch a moving default branch. Is the submodule gitlink present?" >&2 + exit 1 +elif sparse_fetch "$PIN"; then : -elif [ -n "$PIN" ] && sparse_fetch ""; then - echo "note: pinned commit unavailable; fetched default-branch tip instead" >&2 else - echo "sparse fetch failed; falling back to a full submodule update" >&2 - rm -rf "${SUBMODULE_PATH:?}/.git" - git -C "$SUPER_DIR" submodule update --init --depth 1 "$SUBMODULE_REL" + # The fast partial+sparse fetch of the pinned SHA didn't work (e.g. an old + # git, or a server that refuses a blob:none fetch of a non-tip SHA). Fall + # back to a correct, still *pinned* full fetch (slower — it pulls the whole + # gcc tree at that commit — but it tests exactly the pin). + echo "sparse fetch of pinned commit $PIN failed; doing a full (pinned) fetch" >&2 + full_fetch "$PIN" || { + echo "error: could not fetch pinned gcc-testsuite commit $PIN" >&2 + exit 1 + } fi # Fetch the few out-of-tree files torture tests #include (gcc.dg/, gcc.target/) From 9b4589b41c452694fa3f6bb25311846d7a73de70 Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 16:47:52 +0200 Subject: [PATCH 04/22] gcc-torture: bump pinned gcc to cbc56384; handle the new tests Pin gcc-testsuite at a fixed recent commit so CI is reproducible instead of drifting. The bump adds 18 torture tests; handle the ones this tcc can't pass: - skip the *-builtin-issignaling-1 family via should_skip_gcc_test: they need the unimplemented __builtin_issignaling (and __bf16/_Float16/_Float128 types) - xfail pr125291: a confirmed codegen miscompile (wrong result at every -O level), not an unsupported feature, so a future fix surfaces as an XPASS The remaining new tests (pr122000, pr124358, six compile PRs) and all 78 modified existing tests pass under QEMU. Co-Authored-By: Claude Opus 4.8 (1M context) --- tests/gcctestsuite/conftest.py | 12 ++++++++++++ tests/gcctestsuite/gcc-testsuite | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/tests/gcctestsuite/conftest.py b/tests/gcctestsuite/conftest.py index fc576613..2cec570e 100644 --- a/tests/gcctestsuite/conftest.py +++ b/tests/gcctestsuite/conftest.py @@ -88,6 +88,12 @@ def get_opt_levels(env_var: str = "YASOS_TCC_TEST_OPT_LEVELS", *, default: tuple # builtins/ tests — builtin override tests requiring lib/main.c framework # compile/ tests — compilation failures (parser, type system, unsupported features) # always_inline related failures (need proper fix for inline expansion) + # Confirmed real miscompile (not an unsupported feature): the function + # computes the wrong result at every -O level (xfail rather than skip so a + # future codegen fix shows up as an XPASS). Minimal repro: a while loop with + # `(short)` truncation, an unsigned-char shift count (`flagbyte >> flagbits`) + # and `& 3`; tcc returns 3 at -O0 and 2 at -O1/-O2 instead of 1. + "pr125291", } # GCC Torture tests expected to fail only at -O1 @@ -309,6 +315,12 @@ def should_skip_gcc_test(test_path: Path) -> Optional[str]: import re as _re skip_patterns = { "mipscop", + # __builtin_issignaling is not implemented by this tcc, so the gcc + # *-builtin-issignaling-1 torture family (plain plus the _Float16/ + # _Float32/_Float64/_Float128/__bf16 variants, which also need those + # types) fails to compile with "implicit declaration". Skip on the + # feature token so future variants are covered automatically. + "__builtin_issignaling", } name = test_path.name.lower() diff --git a/tests/gcctestsuite/gcc-testsuite b/tests/gcctestsuite/gcc-testsuite index 987dc2c4..cbc56384 160000 --- a/tests/gcctestsuite/gcc-testsuite +++ b/tests/gcctestsuite/gcc-testsuite @@ -1 +1 @@ -Subproject commit 987dc2c4824dc45a775128ccdcaed66d1ada11b4 +Subproject commit cbc56384029c9224280b0a1018fb9502797f243d From a485fa93f47d296317e5da8037b60ee0730027cc Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 16:47:52 +0200 Subject: [PATCH 05/22] ci: upload debug artifacts when make test fails On failure, tee the full make-test log and emit a JUnit report, then bundle for download: the log, the JUnit report, the built cross compiler + runtime (armv8m-tcc / armv8m-libtcc1.a / config.mak), and only the work dirs of the tests that actually failed (mapped from JUnit to pytest's tmp-dir names, so the ~13k-case suite isn't uploaded wholesale). Lets CI-only miscompiles be reproduced locally. Co-Authored-By: Claude Opus 4.8 (1M context) --- .github/workflows/ci.yml | 27 ++++++- scripts/collect_ci_failure_artifacts.sh | 96 +++++++++++++++++++++++++ 2 files changed, 122 insertions(+), 1 deletion(-) create mode 100755 scripts/collect_ci_failure_artifacts.sh diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4f6336fc..bd241e2d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -29,7 +29,32 @@ jobs: - name: Build and test shell: bash + env: + # Write a JUnit report from every pytest run (the final ir_tests run + # overwrites it last) so the failure collector knows which tests failed. + PYTEST_ADDOPTS: "--junitxml=/tmp/ci-junit.xml" run: | virtualenv .venv source .venv/bin/activate - make test -j$(nproc) + # `shell: bash` runs with -eo pipefail, so a failing make still fails + # the step even though its output is teed to a log we upload on failure. + make test -j$(nproc) 2>&1 | tee /tmp/make-test.log + + - name: Collect failure artifacts + if: failure() + shell: bash + env: + MAKE_TEST_LOG: /tmp/make-test.log + PYTEST_JUNIT_XML: /tmp/ci-junit.xml + run: | + source .venv/bin/activate 2>/dev/null || true + bash scripts/collect_ci_failure_artifacts.sh "$PWD/ci-failure-artifacts" + + - name: Upload failure artifacts + if: failure() + uses: actions/upload-artifact@v4 + with: + name: make-test-failure-artifacts + path: ci-failure-artifacts.tar.gz + retention-days: 14 + if-no-files-found: warn diff --git a/scripts/collect_ci_failure_artifacts.sh b/scripts/collect_ci_failure_artifacts.sh new file mode 100755 index 00000000..b51bc771 --- /dev/null +++ b/scripts/collect_ci_failure_artifacts.sh @@ -0,0 +1,96 @@ +#!/usr/bin/env bash +# Gather a compact debug bundle after a failing `make test`, for CI to upload as +# an artifact (see .github/workflows/ci.yml). It captures: +# +# * make-test.log — the full (untruncated) build+test console output +# * junit.xml — the structured pass/fail report +# * armv8m-tcc, armv8m-libtcc1.a, config.mak — the exact cross compiler + +# runtime that produced the failure, so it can be reproduced locally +# * failed-test-dirs/ — ONLY the per-test work dirs (.elf/.o/...) of the tests +# that actually failed. pytest keeps every test's tmp dir, which for the +# ~13k-case torture suite is far too large to upload wholesale, so we map +# each failed JUnit testcase to its tmp-dir prefix and copy just those. +# +# Best-effort throughout: a missing piece is skipped, never fatal, so the +# bundle is produced even when the build failed before any test ran. +set -uo pipefail + +TOP="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)" +OUT="${1:-$TOP/ci-failure-artifacts}" +LOG="${MAKE_TEST_LOG:-/tmp/make-test.log}" +JUNIT="${PYTEST_JUNIT_XML:-/tmp/ci-junit.xml}" +BASETEMP_ROOT="${PYTEST_BASETEMP_ROOT:-/tmp/pytest-of-root}" +MAX_TESTDIR_BYTES="${MAX_TESTDIR_BYTES:-209715200}" # 200 MB cap on collected tmp dirs + +rm -rf "$OUT" +mkdir -p "$OUT" + +# 1) Logs / reports. +[ -f "$LOG" ] && cp "$LOG" "$OUT/make-test.log" || true +[ -f "$JUNIT" ] && cp "$JUNIT" "$OUT/junit.xml" || true + +# 2) The cross compiler + runtime + build config. +for f in armv8m-tcc armv8m-tcc.exe armv8m-libtcc1.a config.mak; do + [ -f "$TOP/$f" ] && cp "$TOP/$f" "$OUT/" || true +done + +# 3) Work dirs of the failed tests only. +if [ -f "$OUT/junit.xml" ] && [ -d "$BASETEMP_ROOT" ]; then + python3 - "$OUT/junit.xml" "$BASETEMP_ROOT" "$OUT/failed-test-dirs" "$MAX_TESTDIR_BYTES" <<'PY' || true +import os, re, shutil, sys, xml.etree.ElementTree as ET + +junit, basetemp_root, dest, max_bytes = sys.argv[1:5] +max_bytes = int(max_bytes) + +try: + root = ET.parse(junit).getroot() +except Exception as e: + print(f"collect: could not parse junit ({e})", file=sys.stderr) + sys.exit(0) + +# pytest names a test's tmp dir from re.sub(r"\W","_", node_name)[:30] + a number. +prefixes = { + re.sub(r"\W", "_", tc.get("name", ""))[:30] + for tc in root.iter("testcase") + if tc.find("failure") is not None or tc.find("error") is not None +} +if not prefixes: + print("collect: no failed testcases in junit") + sys.exit(0) + +def dir_size(p): + total = 0 + for r, _, files in os.walk(p): + for f in files: + fp = os.path.join(r, f) + if not os.path.islink(fp) and os.path.exists(fp): + total += os.path.getsize(fp) + return total + +os.makedirs(dest, exist_ok=True) +total = copied = 0 +for run in sorted(os.listdir(basetemp_root)): + run_dir = os.path.join(basetemp_root, run) + if not os.path.isdir(run_dir): + continue + for d in sorted(os.listdir(run_dir)): + src = os.path.join(run_dir, d) + if not os.path.isdir(src) or not any(d.startswith(p) for p in prefixes): + continue + sz = dir_size(src) + if total + sz > max_bytes: + print(f"collect: 200MB cap reached at {total} bytes; skipping remaining dirs", + file=sys.stderr) + print(f"collect: copied {copied} failed-test dir(s), {total} bytes") + sys.exit(0) + shutil.copytree(src, os.path.join(dest, f"{run}__{d}"), dirs_exist_ok=True) + total += sz + copied += 1 +print(f"collect: copied {copied} failed-test dir(s), {total} bytes") +PY +fi + +# 4) One archive for upload. +( cd "$(dirname "$OUT")" && tar czf "$(basename "$OUT").tar.gz" "$(basename "$OUT")" ) || true +echo "collect: bundle at $OUT.tar.gz" +ls -la "$OUT" 2>/dev/null || true From 76fa701bd09c1fac0b86c31549b3b809fc4f6c81 Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 18:06:22 +0200 Subject: [PATCH 06/22] fixed bug and added unit tests --- CLAUDE.md | 2 +- Makefile | 19 +- configure | 11 +- docs/SESSION_HANDOFF_optimizer_tests.md | 82 ++++ docs/plan_binary_size_reduction.md | 229 +++++++++++ docs/plan_bug_hunting.md | 100 +++++ docs/plan_corner_case_tests.md | 89 +++++ docs/plan_optimizer_test_coverage.md | 168 ++++++++ ir/opt_loop_utils.c | 9 +- ir/ssa.c | 60 ++- tccgen.c | 23 ++ tests/gcctestsuite/conftest.py | 6 - tests/unit/PASS_COVERAGE.md | 121 ++++++ tests/unit/arm/armv8m/Makefile | 42 +- tests/unit/arm/armv8m/ir_build.h | 105 +++++ tests/unit/arm/armv8m/stubs.c | 49 +++ tests/unit/arm/armv8m/test_main.c | 22 ++ tests/unit/arm/armv8m/test_opt_cmp_fuse.c | 260 +++++++++++++ tests/unit/arm/armv8m/test_opt_cmpfold.c | 172 +++++++++ tests/unit/arm/armv8m/test_opt_constfold.c | 254 ++++++++++++ tests/unit/arm/armv8m/test_opt_constprop.c | 364 ++++++++++++++++++ tests/unit/arm/armv8m/test_opt_copyprop.c | 266 +++++++++++++ .../unit/arm/armv8m/test_opt_dead_lea_store.c | 188 +++++++++ tests/unit/arm/armv8m/test_opt_jump_thread.c | 269 +++++++++++++ tests/unit/arm/armv8m/test_opt_knownbits.c | 242 ++++++++++++ tests/unit/arm/armv8m/test_opt_licm.c | 276 +++++++++++++ tests/unit/arm/armv8m/test_opt_neg_chain.c | 114 ++++++ .../unit/arm/armv8m/test_opt_setif_or_taut.c | 197 ++++++++++ tests/unit/ut.h | 6 + 29 files changed, 3717 insertions(+), 28 deletions(-) create mode 100644 docs/SESSION_HANDOFF_optimizer_tests.md create mode 100644 docs/plan_binary_size_reduction.md create mode 100644 docs/plan_bug_hunting.md create mode 100644 docs/plan_corner_case_tests.md create mode 100644 docs/plan_optimizer_test_coverage.md create mode 100644 tests/unit/PASS_COVERAGE.md create mode 100644 tests/unit/arm/armv8m/ir_build.h create mode 100644 tests/unit/arm/armv8m/test_opt_cmp_fuse.c create mode 100644 tests/unit/arm/armv8m/test_opt_cmpfold.c create mode 100644 tests/unit/arm/armv8m/test_opt_constfold.c create mode 100644 tests/unit/arm/armv8m/test_opt_constprop.c create mode 100644 tests/unit/arm/armv8m/test_opt_copyprop.c create mode 100644 tests/unit/arm/armv8m/test_opt_dead_lea_store.c create mode 100644 tests/unit/arm/armv8m/test_opt_jump_thread.c create mode 100644 tests/unit/arm/armv8m/test_opt_knownbits.c create mode 100644 tests/unit/arm/armv8m/test_opt_licm.c create mode 100644 tests/unit/arm/armv8m/test_opt_neg_chain.c create mode 100644 tests/unit/arm/armv8m/test_opt_setif_or_taut.c diff --git a/CLAUDE.md b/CLAUDE.md index d6e0f105..5304fc25 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -10,7 +10,7 @@ This is a specialized fork of **TinyCC (Tiny C Compiler)** targeting **ARMv8-M** ```bash # One-time setup -./configure +./configure # AddressSanitizer is ON by default; ./configure --disable-asan for fast/production builds make download-gcc-tests # optional: sparse-fetch GCC torture tests (~16 MB, not the full gcc repo) # Build ARMv8-M cross compiler diff --git a/Makefile b/Makefile index 937648f4..9ce4a6dd 100644 --- a/Makefile +++ b/Makefile @@ -164,6 +164,13 @@ CHECKSUM_CMD = $(shell command -v sha256sum 2>/dev/null || command -v md5sum 2>/ # proceed while still keeping ASan instrumentation. ifeq ($(CONFIG_asan),yes) SAN_ENV = LSAN_OPTIONS=detect_leaks=0 ASAN_OPTIONS=detect_leaks=0 +# TinyCC (like most compilers) intentionally does not free everything on exit, +# so LSan's at-exit leak check would make every compiler invocation — including +# each test compile under `make test` — exit non-zero. Default leak detection +# off (ASan still catches buffer overflows / use-after-free); override by +# exporting your own [AL]SAN_OPTIONS. +export LSAN_OPTIONS ?= detect_leaks=0 +export ASAN_OPTIONS ?= detect_leaks=0 endif @@ -338,18 +345,26 @@ endif gcc -DC2STR $(filter %.c,$^) -o c2str.exe && ./c2str.exe $< $@ # target specific object rules -$(X)%.o : %.c $(LIBTCC_INC) +# (depend on config.mak so toggling build flags — e.g. ASan via +# ./configure [--disable-asan] — forces a recompile instead of silently +# relinking stale, differently-instrumented objects) +$(X)%.o : %.c $(LIBTCC_INC) config.mak $S$(CC) -o $@ -c $< $(addsuffix ,$(DEFINES) $(CFLAGS)) # Architecture library — built by nested Makefile TARGET_ARCH_NAME = $($T_ARCH) $(ARCH_LIB): FORCE @mkdir -p $(dir $(ARCH_LIB)) + @# Build flags changed (e.g. ASan toggled via configure)? Drop stale objects + @# since the nested arch Makefile only tracks source timestamps, not flags. + @if [ -f "$(ARCH_LIB)" ] && [ config.mak -nt "$(ARCH_LIB)" ]; then \ + rm -f $(dir $(ARCH_LIB))*.o "$(ARCH_LIB)"; \ + fi $S$(MAKE) --no-print-directory -C arch ARCH=$(TARGET_ARCH_NAME) \ TOP=$(CURDIR) BUILD_DIR=$(CURDIR)/$(dir $(ARCH_LIB)) \ CC="$(CC)" AR="$(AR)" CFLAGS="$(CFLAGS)" DEFINES="$(DEFINES)" -$(X)ir/%.o : ir/%.c $(LIBTCC_INC) +$(X)ir/%.o : ir/%.c $(LIBTCC_INC) config.mak @mkdir -p $(dir $@) $S$(CC) -o $@ -c $< $(addsuffix ,$(DEFINES) $(CFLAGS)) diff --git a/configure b/configure index 09ba2b30..70abb093 100755 --- a/configure +++ b/configure @@ -172,6 +172,8 @@ for opt do ;; --enable-asan) confvars_set asan ;; + --disable-asan) asan_disabled=yes + ;; --enable-ubsan) confvars_set ubsan ;; --enable-lsan) confvars_set lsan @@ -195,6 +197,12 @@ for opt do esac done +# AddressSanitizer is enabled by default for this fork; opt out with +# --disable-asan (e.g. for fast production / firmware builds). +if test "$asan_disabled" != "yes"; then + confvars_has asan || confvars_set asan +fi + show_help() { cat << EOF Usage: configure [options] @@ -223,7 +231,8 @@ Advanced options (experts only): --extra-ldflags= specify linker options [$LDFLAGS] --debug include debug info with resulting binaries - --enable-asan enable AddressSanitizer (ASan) + --enable-asan enable AddressSanitizer (ASan) [default] + --disable-asan disable AddressSanitizer (ASan) --enable-ubsan enable UndefinedBehaviorSanitizer (UBSan) --enable-lsan enable LeakSanitizer (LSan) --enable-O0 disable optimizations (GCC -O0) diff --git a/docs/SESSION_HANDOFF_optimizer_tests.md b/docs/SESSION_HANDOFF_optimizer_tests.md new file mode 100644 index 00000000..6f56c25b --- /dev/null +++ b/docs/SESSION_HANDOFF_optimizer_tests.md @@ -0,0 +1,82 @@ +# Session handoff — tinycc optimizer-pass unit tests + +Paste the "Kickoff prompt" below into a fresh session. Everything it references is in the repo. + +--- + +## Context / goal +Part of the tinycc flash-size-reduction effort: before merging the legacy linear-IR optimizer +into the SSA optimizer, every optimization pass needs isolated host unit tests so the merge can't +silently regress codegen. Plan: `libs/tinycc/docs/plan_optimizer_test_coverage.md`. Live tracker: +`libs/tinycc/tests/unit/PASS_COVERAGE.md`. Harness how-to memory: `yasos-tcc-optpass-unit-test-harness`. + +**Working rules (hard):** write tests in parallel to bug-fixing; **do NOT modify production code** +(anything under `ir/`, or root `tcc*.c`/`*.h`). If a test surfaces a bug, record it under *Findings* +in PASS_COVERAGE.md with a minimal repro — do not fix it. + +## State at handoff +- Harness foundation done: `tests/unit/arm/armv8m/ir_build.h` (hand-built IR), `UT_COVERS()` in `ut.h`, + Makefile uses `-ffunction-sections -fdata-sections` + `-Wl,--gc-sections` to pull `irop_config` + out of heavy `ir/core.c` without dragging frontend symbols. +- Shared base modules already wired into the Makefile: `ir/opt.c`, `ir/opt_alias.c`, `ir/cfg.c`, + plus a `get_tok_str` stub in `stubs.c`. +- `make ut` is GREEN at **524 tests**. Only `opt_neg_chain` (4) among the new suites is registered. +- **10 more suites (65 tests) are written and each was self-verified GREEN in isolation, but are NOT + yet registered** in `test_main.c` / the Makefile, so they don't run in `make ut`/`make test` yet. +- `make test` runs `ut` as a prerequisite (Makefile:667) and a unit-test failure fails `make test`. + +Test files on disk (all under `tests/unit/arm/armv8m/`): test_opt_neg_chain.c *(registered)*, +test_opt_knownbits.c, test_opt_copyprop.c, test_opt_cmp_fuse.c, test_opt_cmpfold.c, +test_opt_constprop.c, test_opt_constfold.c, test_opt_licm.c, test_opt_jump_thread.c, +test_opt_setif_or_taut.c, test_opt_dead_lea_store.c. + +## IMMEDIATE TASK — register the 10 verified suites (mechanical) +1. **stubs.c**: add `void *elfsym(void *s){ (void)s; return 0; }` (needed by `ir/opt_dce.c` for the cmpfold suite; benign for hand-built IR). +2. **Makefile `UT_MODULE_SRCS`** — add (de-duplicated): + `ir/opt_knownbits.c ir/opt_copyprop.c ir/opt_cmp_fuse.c ir/opt_constprop.c ir/opt_du.c ir/opt_constfold.c ir/licm.c ir/opt_jump_thread.c ir/opt_setif_or_taut.c ir/opt_dead_lea_store.c ir/opt_dce.c` +3. **Makefile `UT_LOCAL_SRCS`** — add the 10 `test_opt_*.c` files listed above. +4. **test_main.c** — `UT_DECLARE_SUITE` + `UT_RUN_SUITE` for: opt_knownbits, opt_copyprop, opt_cmp_fuse, + opt_cmpfold, opt_constprop, opt_constfold, opt_licm, opt_jump_thread, opt_setif_or_taut, opt_dead_lea_store. +5. `make ut` → expect **~589 tests, 0 failed**. + +### Gotchas for the combined link (the real test is the union build) +- Each suite was verified individually against the same base, so the union should resolve — but the + combined `make ut` is the proof. If it fails, it's almost certainly a **duplicate symbol** or an + **undefined ref** not seen per-suite. +- `test_opt_constfold.c` defines 4 frontend link-stubs in-file (`global_stack`, `sym_push2`, + `external_global_sym`, `tok_alloc_const`). If another newly-linked module also defines one, you'll get + a duplicate-symbol error — move those stubs to `stubs.c` (shared) to resolve. +- The session-scratch self-verify tool (`verify_suite.sh` + `utbase/`) lived in `/tmp/.../scratchpad/` + and is **gone in a new session**. Don't look for it — just use `make ut` to verify the integrated build. + (If you want per-suite isolation again, the recipe is in PASS_COVERAGE.md and the harness memory.) + +## Findings so far +- **No production bugs found.** All suites are *characterization* tests (expectations derived from the + code) — a good regression baseline for the merge, but weak at *finding* bugs. The smoke/QEMU suite + remains the stronger oracle. +- One harness limitation: name-gated constfold passes (`self_copy_elim`, `float_narrowing`) can't reach + their positive fold because the `get_tok_str` stub returns a constant — they're covered as guard-only. + +## After integration — phases (see PASS_COVERAGE.md for the full list) +- **Highest bug-finding value:** legacy-vs-SSA **equivalence harness** (run both pass paths on the same IR, + assert identical results) — Phase F. Also spec-oracle asserts (compute expected fold in the test) and + edge/fuzz inputs (overflow, width boundaries, merge points, back-edges). +- Phase C: SSA passes (`ssa_opt_*`) via golden-IR snapshots. +- Phase D: codegen size levers via objdump pattern/count (R9 spills, b.w→b.n, cbz). +- Phase E: `check_pass_coverage.py` ledger gating `UT_COVERS` vs registered passes in CI. +- Phase F: remaining uncovered entries in multi-pass files (copyprop/constprop/constfold ~15 more); + deferred: `opt_switch_data` (needs section/codegen state). + +--- + +## Kickoff prompt (paste into the new session) +> Continue the tinycc optimizer-pass unit-test work. Read `libs/tinycc/tests/unit/PASS_COVERAGE.md` +> and `libs/tinycc/docs/SESSION_HANDOFF_optimizer_tests.md` first. Do NOT modify production code; if a +> test reveals a bug, record it under *Findings* in PASS_COVERAGE.md, don't fix it. +> Immediate task: register the 10 already-written, isolation-verified suites into the build — add the +> `elfsym` stub to stubs.c, add the pass sources to `UT_MODULE_SRCS`, add the test files to +> `UT_LOCAL_SRCS`, and declare+run the 10 suites in test_main.c. Then run `make ut` and confirm it goes +> from 524 to ~589 tests, 0 failed (watch for duplicate-symbol / undefined-ref issues in the combined +> link; if the 4 frontend stubs in test_opt_constfold.c collide, move them to stubs.c). Update +> PASS_COVERAGE.md to mark the suites integrated. After that, propose the legacy-vs-SSA equivalence +> harness (Phase F) as the next bug-finding step. diff --git a/docs/plan_binary_size_reduction.md b/docs/plan_binary_size_reduction.md new file mode 100644 index 00000000..38aea47f --- /dev/null +++ b/docs/plan_binary_size_reduction.md @@ -0,0 +1,229 @@ +# Plan: Shrink on-device `tcc` from 2.17 MiB → ~1 MB + +## Context + +The self-hosted on-device compiler `rootfs/usr/bin/tcc` has grown to **2.17 MiB of +`.text`** (2,270,264 B; `.rodata` ~99 KB). It no longer fits the size budget; the +goal is ~1 MB. + +This plan is about the **size of the compiler binary itself**. It is complementary +to `plan_closing_gcc_gap.md` (which targets per-function codegen quality via +whole-program inlining / const-fold) — improvements there also shrink this binary, +since `tcc` is built by compiling its own source with `tcc -O2`. + +### Measured root causes + +Reproducible by compiling each native TU two ways and comparing `.text` +(`arm-none-eabi-size`): the cross `armv8m-tcc` is byte-identical codegen to the +on-device binary, vs `arm-none-eabi-gcc -O2 -mcpu=cortex-m33 -mthumb -mfloat-abi=hard`. + +**1. Codegen quality gap — tcc emits 1.48× more code than gcc-O2, 2.29× more than +gcc-Os** (e.g. `tccgen.c`: tcc 326 KB / gcc-O2 198 KB / gcc-Os 142 KB). Dominated by +mechanical backend issues: + +| Issue | Count | Cost | Note | +|---|---|---|---| +| R9 GOT-base save/restore around every call | 39,858 `str` + 39,827 `ldr` | **~311 KB (13.7% of `.text`)** | R9 is function-invariant; pre-call stores are redundant | +| `cmp #0;b{eq,ne}` not fused to `cbz/cbnz` | 21,833 sites | ~42 KB | fusion code exists but is **disabled** (forward-range soundness) | +| Pessimistic wide `b{cond}.w` | 58,611 sites | tens of KB | forward branches never narrowed | + +**2. Code volume — the optimizer is ~39% of the binary.** Two parallel frameworks +with overlapping work: legacy linear-IR passes (`ir/opt_*.c`, 37 files, **752 KB**, +a 108-pass pipeline) + SSA passes (`ir/opt/ssa_opt_*.c`, 15 files, **131 KB**, run at +regalloc time). + +### Category breakdown of `.text` (tcc vs gcc-O2, per-TU) + +| Category | tcc | gcc | ratio | +|---|---:|---:|---:| +| opt — legacy linear-IR (37 files) | 752 KB | 576 KB | 1.34 | +| arm backend (`arm-thumb-gen` + `arch/`) | 327 KB | 195 KB | 1.68 | +| `tccgen` front-end | 326 KB | 198 KB | 1.64 | +| codegen + regalloc | 138 KB | ~95 KB | ~1.5 | +| opt — SSA (`ir/opt/`, 15 files) | 131 KB | 93 KB | 1.44 | +| preprocessor / elf+link / asm / debug-gen | ~190 KB | ~125 KB | ~1.5 | + +### Decision & realistic math + +Pursue the **full path to 1 MB**, including the legacy→SSA optimizer +consolidation (high-risk, in a fork with a history of subtle opt miscompiles). +Phases 1–3 ≈ 400–450 KB at low risk (→ ~1.6 MB); the `-Os` self-host build is +potentially large; Phase 4's deletable slice ≈ 200–300 KB (the `opt_dead_*` / +`opt_gens_*` families are **lowering/machine-prep that must stay**). Reaching 1 MB +requires all of them landing. + +Validation = QEMU smoke + gcc-torture + size measurement, **gated in CI with a +Grafana dashboard** (user-hosted server) tracking size + compile-perf per commit. + +**Correctness coverage is a hard prerequisite, not just validation.** Smoke + +torture catch *many* miscompiles but corner cases slip through (the fork's history +of pass-local defects). Before the high-risk optimizer work, build the host-side +per-pass + codegen test layer described in **`plan_optimizer_test_coverage.md`** +(isolated `ut.h` unit tests for legacy passes, golden-IR snapshots for SSA passes, +objdump pattern/count tests for codegen). It is the **gate for Phase 4** and +regression-locks the Phase 1–3 codegen wins. + +--- + +## Phase 0 — Metrics harness + CI size-gate + Grafana (foundation, do first) + +**Goal:** make every later change measurable and regression-gated before touching +codegen. + +**Reuse, don't rebuild:** `scripts/disasm_common.py` already compiles TCC+GCC, +disassembles with a best-known-result cache (`.disasm_cache.json` / +`.pending.json`), counts instructions, and compares per-function TCC-vs-GCC size. +`scripts/compare_disasm.py` / `scripts/regression_disasm.py` drive it. + +**Build:** +- New `scripts/size_metrics.py` on top of `disasm_common`: emit a JSON record per + build — total `.text`/`.rodata` of `bin/armv8m-tcc.elf` (`arm-none-eabi-size`), + per-category `.text` (the category map above), per-TU tcc-vs-gcc ratio, the + R9-spill / cbz-candidate / wide-branch instruction counts (objdump greps), and a + representative compile-time sample (reuse the on-target per-pass timing where + available). Key by git SHA + timestamp. +- Time-series + dashboard on the user's server: stand up **InfluxDB** (or + **Prometheus + Pushgateway**) + **Grafana**; `size_metrics.py --push` writes the + record. Grafana board: total `.text` over time (target line at 1.0 MB), + per-category stacked area, tcc/gcc ratio, compile time. +- CI: add a `size_metrics` job to `.github/workflows/yasos_smoke.yml` (after + `qemu_gate`, parallel to `build_hw`) that builds the cross + self-host tcc, runs + `size_metrics.py --push`, and **fails the PR if total `.text` regresses beyond a + small threshold** vs the `main` baseline. + +**Verify:** dashboard shows the current 2.17 MiB baseline; a no-op rebuild +reproduces it; an intentional +bloat test trips the gate. + +--- + +## Phase 1 — R9 GOT-base save/restore (~150 KB → up to ~300 KB) + +All logic is in `tcc_gen_machine_func_call_mop()` — `arm-thumb-gen.c:11711-11974`. +R9 is added to the per-call save mask at `:11760-11761`, stored at `:11776-11791` +(to `[SP + ir->call_outgoing_size + slot]`), reloaded at `:11932-11963` (with the +`allow_r9_write` gate). R9 is **not** materialized in the prologue today (the +runtime linker sets it — `arm-link.c:144-223`). Prologue builder: +`tcc_gen_machine_prolog()` `:9396-9700`. Note `caller_saved_registers` (`:210`, set +`:2422-2428`) is **dead** (never read) — clean up. + +**Phase 1a (low risk, ~150 KB):** store R9 once to a fixed reserved frame slot in +the prologue; remove R9 from `arg_regs_save_mask` (drop all pre-call stores); +repoint the post-call reload at that fixed slot. Requires reserving one word in the +frame layout (`ir/stack.c`). Net: 1 store + N reloads instead of N + N. + +**Phase 1b (medium risk, +~120 KB):** hold the GOT base in a callee-saved register +(e.g. r10 — AAPCS-compliant callees preserve it) reserved out of +`registers_map_for_allocator` (`:2417-2418`). Replace post-call `ldr.w r9,[sp]` +(4 B) with `mov r9, r10` (2 B), eliminating the slot and halving reload cost. +Further: skip the restore entirely after **intra-module** (static, non-PLT) calls, +where R9 is provably unchanged. + +**Verify:** the `allow_r9_write` guard (`:2918-2923`) must stay green (no stray R9 +writes); QEMU smoke + torture at -O0/-O1/-O2; `size_metrics.py` shows the R9-spill +instruction count drop toward 0. + +--- + +## Phase 2 — Branch peepholes (~80 KB) + +Two-pass dry-run/real-run codegen in `ir/codegen.c:2344-4385`; relaxation infra +`branch_opt_analyze()` at `arm-thumb-gen.c:1019-1251`, called post-dry-run at +`ir/codegen.c:4212`. Conditional branch emit: +`tcc_gen_machine_conditional_jump_mop()` `:12029-12051` (backward already narrowed +via `can_narrow_backward_branch()` `:11981-12004`; forward always wide). CBZ builder +`th_cbz` exists (`arch/arm/thumb/thop_branch.c:146-217`); fusion peephole present but +**disabled** at `ir/codegen.c:2351-2371, 2590-2631, 2806-2850`; patch/abort path +`:3224-3285`. See `codegen_dry_run_opt.md` for the two-pass design. + +**Phase 2a (~38 KB):** extend `branch_opt_analyze()` to narrow **forward** +conditional branches too — the dry-run layout map already gives final offsets, so +feed forward targets through the same relaxation decision. + +**Phase 2b (~42 KB):** re-enable CBZ/CBNZ fusion by making relaxation +**re-materialize out-of-range CBZ as `cmp #0;b{eq,ne}`** during the fixpoint, +removing the commitment hazard the disabled code documents. + +**Verify:** the branch-relaxation fixpoint must converge (assert no size +oscillation); smoke + torture (branch-heavy tests); metrics show wide-branch + +cbz-candidate counts drop. + +--- + +## Phase 3 — Build / feature levers (~100–200 KB, low effort) + +- **Self-host at `-Os`:** the on-device tcc is built at `-O2` (`build_rootfs.sh` + `NATIVE_TCC_DEBUG_OPT=-O2`, ~line 296). An `-Os` IR pipeline already exists + (`ir/opt_pipeline.c:539-557` skips the fusion group). Set + `NATIVE_TCC_OPT_OVERRIDE=-Os`, rebuild, measure — likely the single biggest cheap + win (gcc -Os was 1.4× smaller than gcc-O2 here). Tune the `-Os` pipeline to also + drop unroll/reroll. +- **Drop `-DCONFIG_TCC_DEBUG`** from the production self-host build (removes + `-dump-ir` machinery) once on-device IR dumping is no longer needed. +- **Gate on-device debug-info emission** (`tccdbg`/`tccdebug`, ~30 KB `.text`) and + the **inline assembler** (`tccasm`, ~20 KB, 2.07× ratio) behind a config if + unused on device. + +**Verify:** the `-Os` self-host must still pass full smoke + torture (codegen-mode +change — watch for latent -Os miscompiles); confirm debug/asm features are truly +unused before gating. + +--- + +## Phase 4 — Optimizer consolidation: legacy → SSA (~200–300 KB, high risk, the 1 MB-maker) + +**Prerequisite (gate):** do not start until the per-pass + merge-equivalence coverage +from `plan_optimizer_test_coverage.md` exists for the passes this phase touches. Each +"disable → delete" step below then runs the fast legacy↔SSA equivalence diff *before* +the slow QEMU smoke/torture gate. + +Legacy pipeline: `ir/opt_pipeline.c` (groups at `:522-566`, O-level gate +`:539-557`), engine `ir/opt_engine.{h,c}` (static `PASS()` arrays — remove a pass by +deleting its array entry or gating its `flag_offset`). SSA run: +`ir/regalloc.c:3991-4030` → driver `ir/opt/ssa_opt.c:648-703`. Background: +`plan_ssa.md`, `plan_ssa_regalloc.md`, `plan_opt_modularization.md`, `plan_opt_split.md`. + +**Pass classification (from code exploration):** +- **Delete once SSA confirmed equivalent:** `opt_constprop.c` (→ `ssa_opt_sccp`), + `opt_copyprop.c` (→ `ssa_opt_cprop` + `ssa_opt_dce`), `opt_branch.c` basic folding + (→ `ssa_opt_sccp` + `ssa_opt_branch`), `opt_loop_dead.c` (→ `ssa_opt_dead_loop`). +- **Needs SSA extended first:** `opt_knownbits.c` (SSA fold lacks known-bits + tracking — and it is load-bearing for a known miscompile fix; port carefully), + `opt_loop.c` / `opt_reroll.c` IV strength-reduction (SSA strength is + single-instruction only). +- **MUST KEEP (lowering / machine-prep, not optimization):** all `opt_dead_*.c` + (stack-slot / lval alias analysis — SSA only renames promoted vars, not + address-taken locals / VLAs / param slots) and all `opt_gens_*.c` (ARM + instruction-selection fusion that codegen depends on). + +**Approach (incremental, one pass at a time):** +1. Add a per-pass-family gate flag + a `-disable-legacy-opt` CLI switch so the + SSA-only pipeline can be A/B tested. +2. For each "delete" candidate: disable it, run full smoke + torture + size metrics; + confirm zero correctness regressions and a size drop; then delete the source and + its pipeline entry. +3. Extend SSA (known-bits into `ssa_opt_fold`/`sccp`; loop-IV into + `ssa_opt_strength`) to unlock the "needs-extension" deletions. +4. Leave the lowering / machine-prep families intact. + +**Verify (mandatory per pass removed):** full QEMU smoke **and** gcc-torture at +-O0/-O1/-O2, plus the A/B self-host decisive test (real vs self-host) from +`selfhost_miscompile_debugging.md`; `disasm_common` regression check that no +benchmark function got *worse*; metrics push so the dashboard shows the cumulative +drop. + +--- + +## Overall verification + +- Per change: `size_metrics.py` for immediate `.text` delta + the CI size-gate + (Phase 0). +- Per phase boundary: `make cross && ./build_rootfs.sh` rebuild, then + `./scripts/run_qemu_smoke.sh` (smoke + torture, O0/O1/O2) and hardware smoke on the + RP2350 runner. +- Progress tracked live on the Grafana board against the 1.0 MB target line. + +## Sequencing + +Phase 0 first (foundation). Then 1 → 2 → 3 (independent, low-risk, ~400–600 KB +combined) to reach ~1.6 MB. Then Phase 4 incrementally to close to ~1.0 MB. Phase 1b +and the `-Os` build are the highest size-per-effort items after the gate is in place. diff --git a/docs/plan_bug_hunting.md b/docs/plan_bug_hunting.md new file mode 100644 index 00000000..61887618 --- /dev/null +++ b/docs/plan_bug_hunting.md @@ -0,0 +1,100 @@ +# Plan — real bug hunting for the tinycc optimizer (before legacy↔SSA) + +Goal: actively **find latent miscompiles now**, before the legacy→SSA optimizer merge — +not just lock in current behavior. Slots *before* the legacy↔SSA equivalence work +(Phase F in `plan_optimizer_test_coverage.md`); in fact Track 4 below becomes the +substrate that makes Phase F nearly free. + +## The core principle +The per-pass suites we wrote are **characterization tests**: expectations were derived +from the implementation, so they agree with the code by construction and rarely *find* +bugs. Bug *hunting* requires an **independent oracle** — an expected result computed +without reference to the code under test. Four oracle families below, ordered by ROI. + +Grounding (verified available on this machine): `arm-none-eabi-gcc` ✓, `qemu-system-arm` ✓, +ASAN on by default (`config.mak`) ✓, `csmith` ✗ (not installed — random C must be homegrown +or csmith added). No existing host IR interpreter or real IR verifier (`check_*.c` are +throwaway debug printf programs) — Track 4 builds one. + +**Rules (unchanged):** test/tooling only, **no production edits**. Every confirmed miscompile +→ *Findings* in `PASS_COVERAGE.md` with a minimal repro; hand off to bug-fix work. Differential +failures MUST be triaged for undefined behavior / known-skips before being called bugs. + +--- + +## Track 1 — ASAN + UBSan corpus sweep (memory-safety class) — LOW effort, PROVEN, do first +- Oracle: the sanitizer. Any ASAN/UBSan report during compilation is a bug, full stop. +- Build the x86 cross with ASAN (default) **and** add `-fsanitize=undefined`; compile the whole + corpus (gcc-torture compile + execute, tests2, ir_tests inputs) at `-O0/-O1/-O2`; collect reports. +- Proven technique here — previously found 3 heap overflows (memory `yasos-tcc-asan-sweep-fixes`). +- Deliverable: `scripts/asan_sweep.sh` (corpus × O-levels → grep sanitizer output → dedup by stack). +- Effort ~1 day. Localizes to file:line via backtrace (not always to a pass, but high ROI). +- Parallelizable: shard the corpus across agents. + +## Track 2 — Optimization-level self-consistency differential (miscompile class) — LOW–MED effort, no external oracle +- Oracle: **a program's observable output must be identical at -O0/-O1/-O2.** Divergence ⇒ an + optimization changed behavior ⇒ miscompile. +- Harness: compile each program with tcc at O0/O1/O2 → run under QEMU (reuse ir_tests/mps2-an505 + infra) → diff stdout + exit code. +- Expand coverage with a homegrown **random C generator** (csmith absent): UB-free expressions over + int/uint/char/short/long — arithmetic, bitwise, shifts, comparisons, `if`/`while`/`for`, small + arrays/structs, calls. Print a checksum of computed values so output is sensitive to miscompiles. +- Strength: catches pass + regalloc + codegen *interaction*; pins the offending O-level; no gcc needed. +- Deliverable: `scripts/diff_olevels.py` + `tests/fuzz/gen_c.py`. Effort ~2–3 days. + +## Track 3 — Differential vs arm-none-eabi-gcc (wrong-at-all-levels class) — MED effort, strongest end-to-end +- Oracle: **gcc** (trusted). Same C compiled by tcc (O0/O1/O2) and `arm-none-eabi-gcc -O2`, both run + under the same QEMU harness, compare outputs. +- Catches what Track 2 cannot: bugs where all tcc levels agree but are wrong (frontend/ABI/codegen + constants the optimizer never touched). +- UB trap: only feed UB-free inputs (the generator guarantees it). For the fixed corpus, the + gcc-torture *execute* tests are already self-checking (they `abort()` on wrong results) — run + tcc-compiled torture-execute and treat non-zero exits as candidate miscompiles, then triage against + the known-skip list. This sharpens the existing `test-gcc-torture-execute` into a bug oracle. +- Deliverable: `scripts/diff_vs_gcc.py` (reuses Track 2 plumbing). Effort ~2–3 days. + +## Track 4 — IR metamorphic / semantics-preservation fuzzer (per-pass, host, LOCALIZING) — HIGH effort, the flagship +- The only **host-fast** oracle that pins a bug to **one pass** and a **minimal IR**. Built on `ir_build.h`. +- Components: + 1. `ir_eval.h` — a small reference **interpreter** over the TccIrOp subset: phase 1 arithmetic/logic/ + shift/cmp/assign/zext/ubfx/bfi (straight-line); phase 2 add load/store to a modeled stack; phase 3 + add jump/jumpif/return control flow. Computes a result vector from input register/memory vectors. + 2. `ir_gen.h` — a **random well-formed IR generator** (valid `irop_config` slots, single-def temps, + type-consistent operands, in-range jump targets), seedable via a fixed RNG seed for reproducibility. + 3. Driver `test_metamorphic.c` — for each random fn `f`, each pass `P`, each of N random input vectors: + assert `eval(f) == eval(P(f))`. Mismatch ⇒ `P` miscompiles. Also assert structural invariants after + `P` (operand counts vs `irop_config`, vreg ranges, jump targets in bounds). + 4. **Delta-reducer** — shrink a failing `f` (drop instructions, lower operand magnitudes) while the + mismatch persists → minimal repro for *Findings*. +- Run the whole thing under ASAN (folds in pass-level robustness fuzzing — the byte-drop/OOB class). +- Risk: the evaluator/generator are real code and can have their *own* bugs (false positives). Mitigate: + start with the tiny phase-1 subset; cross-validate `eval()` against QEMU execution on a handful of + hand-written cases; expand incrementally. +- Strength: isolates exact pass + minimal IR, no QEMU, runs in CI in seconds. +- Deliverable: `tests/unit/arm/armv8m/{ir_eval.h,ir_gen.h,test_metamorphic.c}`. Effort ~1–2 weeks, incremental. + +--- + +## Recommended sequencing +1. **Track 1** (ASAN/UBSan sweep) — immediate, proven, parallelizable; flush the memory-safety class first. +2. **Track 2** (O-level diff) — quick win on existing QEMU infra; finds optimization miscompiles end-to-end. +3. **Track 4** (IR metamorphic) — start the evaluator small in parallel; the flagship + the foundation for Phase F. +4. **Track 3** (gcc diff) — cheap once Track 2 plumbing exists; catches the all-levels-agree-but-wrong class. + +## Why this comes before legacy↔SSA (and feeds it) +Phase F equivalence is `eval(legacy(f)) == eval(ssa(f))`. That is **Track 4 with two pipelines instead of +one pass**. Building Track 4's generator + evaluator + reducer now means Phase F is a 1-line variation, and +any bug Tracks 1–4 surface gets fixed *before* the merge muddies attribution. + +## Parallelization map (for a fan-out) +- Track 1: shard corpus across agents; each runs a slice, reports deduped sanitizer hits. +- Track 4: one agent builds `ir_eval.h`, others build `ir_gen.h` op-class generators; then per-pass drivers. +- Tracks 2/3: one harness, then a fleet generating + triaging random programs concurrently. + +## Effort / risk summary +| Track | Oracle | Localizes to | Effort | Notes | +|---|---|---|---|---| +| 1 ASAN/UBSan | sanitizer | file:line | ~1d | proven; memory class only | +| 2 O-level diff | self-consistency | O-level | ~2–3d | needs random C gen (no csmith) | +| 3 gcc diff | arm-none-eabi-gcc | program | ~2–3d | UB triage required | +| 4 IR metamorphic | reference interpreter | **single pass + minimal IR** | ~1–2w | flagship; foundation for Phase F | diff --git a/docs/plan_corner_case_tests.md b/docs/plan_corner_case_tests.md new file mode 100644 index 00000000..f857203d --- /dev/null +++ b/docs/plan_corner_case_tests.md @@ -0,0 +1,89 @@ +# Plan — corner-case unit tests for the optimizer passes + +**Priority (per user, 2026-06-26): do this FIRST**, before the gcc differential (Track 3) and IR +metamorphic fuzzer (Track 4) in `docs/plan_bug_hunting.md`. The 11 integrated suites (Phase B, +`PASS_COVERAGE.md`) cover the happy path + a few guards; this phase systematically drives each pass +into its **edge cases**, where miscompiles actually hide. + +## Principle — make corner cases semi-oracles, not characterization +Where a corner case has an **implementation-independent expected result**, assert that +independently-computed value (not "what the code does"). Then the test can actually *find a bug*: +- e.g. constant-fold of `INT_MIN / -1`, `x << 32`, `INT_MIN` negation, `(uint8_t)0x1F2` — the + correct result is dictated by C/ARM semantics, computed in the test, **not** read from the pass. +- For structural passes (jump-thread, licm, dce) the oracle is an invariant (semantics preserved, + no out-of-range target, converges) rather than a numeric value. + +Rules unchanged: **no production edits**; a confirmed wrong result → *Findings* in `PASS_COVERAGE.md` +with a minimal repro, and assert the **correct** value only if it keeps the suite green; if the pass +is actually wrong, assert current behavior + `/* SUSPECTED BUG */` + Finding (so `make ut` stays green). + +--- + +## A. Cross-cutting corner-case checklist (apply to every pass) +1. **Integer boundaries**: 0, 1, -1, `INT_MIN`, `INT_MAX`, `UINT_MAX`, sign-bit set/clear, powers of two. +2. **Overflow / UB-shaped inputs**: ADD/SUB/MUL 32-bit overflow; `INT_MIN` negation; shift count 0 / 31 / 32 / ≥width / negative; `INT_MIN / -1`; div/mod by 0 (pass must fold-correctly or bail, never crash). +3. **Width & signedness**: INT8/INT16/INT32/INT64; `is_unsigned` on/off; narrow→wide and wide→narrow; mixed-width operands (the historical byte-drop class); zero/sign-extension boundaries. +4. **Degenerate IR**: empty fn; single instruction; all-NOP; NULL ir; max temps (interval-table growth); repeated identical ops. +5. **Control flow** (passes that care): merge point (≥2 preds); back-edge / loop; jump-to-self; target at 0, n-1, and out of range; unreachable block; fallthrough into a labeled target. +6. **Lvalue / memory**: `is_lval` set on dest / src1 / src2 independently; `is_llocal` double-indirection; STORE/LOAD alias (same / overlapping / disjoint byte ranges); address-taken / escaped. +7. **Operand kinds per slot**: immediate vs vreg vs symref vs stackoff; the 4th-operand ops (LOAD_INDEXED/STORE_INDEXED scale, MLA accum, SELECT cond). +8. **Idempotence / fixpoint**: second run returns 0; pass converges; metadata preserved (`orig_index`, `operand_base`, `is_jump_target`, `line_num`). +9. **Robustness**: runs under ASAN clean on all of the above (the suite binary should be built/run under ASAN in CI for this phase). + +--- + +## B. Harness extensions this phase needs (do these before/with the fan-out) +Small additions to `ir_build.h` / a shared helper — needed because corner cases use shapes the current +builder doesn't expose: +- [ ] `utb_emit4(ir, op, dest, src1, src2, op4)` — write the 4th operand at `operand_base+3` (LOAD_INDEXED/STORE_INDEXED scale, MLA accum, SELECT cond) and bump the pool count. +- [ ] `utb_symref(...)` and `utb_stackoff(off, is_lval, is_llocal, is_param, btype)` constructors (for symref_const_prop, dead_lea_store, param/local cases). +- [ ] flag helpers: `utb_lval(op)`, `utb_unsigned(op)`, `utb_llocal(op)` returning a modified copy (cleaner than post-hoc field writes). +- [ ] `utb_run_to_fixpoint(ir, passfn)` — apply until it returns 0; assert convergence. +- [ ] **Settable `get_tok_str` table** (resolves Finding #1): a test-populated token→name map so name-gated constfold passes (`self_copy_elim`, `float_narrowing`, `*_string_calls`, `*_call_replace`) can reach their real positive fold. Replace the constant `"?"` stub with one that reads the table. +- [ ] (optional) a tiny structural sanity checker `utb_assert_wellformed(ir)` — operand counts vs `irop_config`, vreg in range, jump targets in [0,n) — call after each pass in every corner-case test. + +--- + +## C. Per-pass corner-case enumeration +Each item = one (or a few) new test(s) added to that pass's existing `test_opt_*.c`. ★ = likely +bug-revealing semi-oracle (assert an independently-computed value). + +**neg_chain** — chain length 1/2/3/N; ★mixed-width links (INT8↔INT32) must not fold; merge-point reset mid-chain (loop) clears canon; SUB with non-zero minuend; non-temp / VAR operands; reuse after reset; idempotence. + +**known_bits** — AND with 0 / all-ones / partial mask; OR with 0 / all-ones; XOR self; ★SHL/SHR/SAR by 0/31/32 producing fully/partly known; ★narrow load 8/16-bit signed vs unsigned (sign-bit set: 0x80/0x8000); UBFX lsb/width boundaries (lsb 0, width 1, lsb+width=32, lsb+width>32); unknown operand blocks fold; idempotence. + +**const_prop / const_var_prop** — ★`x+0`, `x-0`, `x-x`, `x*0`, `x*1`, `x*2^k`, `x&0`, `x&-1`, `x|0`, `x|-1`, `x^x`, `x^0`; ★`INT_MIN + -1`, `INT_MAX + 1` wrap; ★shift by 0/31/32/neg; ★signed vs unsigned div/mod, `INT_MIN/-1`, div/mod by 0 (must bail, not crash); 64-bit (INT64) folds; immediate not encodable in ARM (large constants); multi-def / addr-taken / non-const guards; idempotence. + +**copy_prop** — copy of copy (chain); ★`is_lval` on src / dest / use in each slot preserved; redefinition between def and use blocks prop; copy across a CALL; copy across a merge point; self-copy; width-mismatch not recorded; STORE-dest pointer rewrite; idempotence. + +**cmp_field_fuse / cmp_expr_fold / cmp_const_offset_fold** — field width 1 and 31; signed vs unsigned compare; offset 0 / negative / overflow; base mismatch; `is_lval` base; CMP not adjacent to the def; ≥3 fields; non-NE/EQ conditions; idempotence. + +**licm** — invariant in a simple loop (positive hoist) ★asserting the moved instr lands in the dominating preheader; nested loop (hoist to the right level); op that is *not* invariant (in-loop def) stays; ★side-effecting op (STORE/CALL/div-by-maybe-0) must NOT hoist; back-edge to index 0; multiple back-edges; no-preheader case; deref/aliasing load not hoisted; straight-line (no loop) → 0; no crash on malformed-ish CFG. + +**jump_threading / eliminate_fallthrough** — chain length 1/2/N; ★cycle A→B→A must terminate (no infinite loop) and not corrupt; jump-to-self; target 0 / n-1 / out of range; conditional vs unconditional; fallthrough across NOPs; backward-edge guard; preserve real branch; idempotence. + +**setif_or_tautology** — every condition code; tautology (always-true) vs contradiction (always-false); ★fold result value (#1 / #0) computed independently; mismatched CMP operands; signed vs unsigned; partial mask union (no fold); SETIF without preceding CMP; idempotence. + +**dead_lea_store_elim** — store then load same / overlapping / disjoint byte ranges (★only disjoint/overwritten is dead); store width vs load width mismatch; address escape (LEA result stored/passed) bails; multiple stores to same slot (earlier dead); no-temp early-out; volatile/lval kept; idempotence. + +**self_copy_elim / float_narrowing** (needs the get_tok_str table from §B) — ★real memcpy/memmove/`__aeabi_mem*` self-copy folds to NOP; non-matching name does not; ★f2d→…→d2f narrowing chain actually narrows (with the name table); partial/!4-instr chains decline; null callee. + +--- + +## D. Execution +- **Fan out one agent per pass** (10–11 agents), each *appending* corner-case tests to its existing + `test_opt_*.c` (distinct files → no write races). Same rules + the `verify`-then-`make ut` discipline. +- Do §B harness extensions **first** (one focused change set) so agents can use `utb_emit4` / flag + helpers / the get_tok_str table. These touch shared files (`ir_build.h`, `stubs.c`) → do serially, not in the fan-out. +- After the fan-out: single `make ut` (expect ~589 → ~150+ more tests), then build+run the unit binary + under ASAN once for the robustness dimension. +- Record every confirmed wrong result in `PASS_COVERAGE.md` *Findings* (do not fix). + +## E. Sequencing +1. §B harness extensions (serial, ~0.5 day). +2. Per-pass corner-case fan-out (parallel, the bulk). +3. ASAN run of the unit binary over the new tests. +4. *Then* Track 3 (gcc diff) and Track 4 (IR metamorphic) from `plan_bug_hunting.md`. + +The arithmetic semi-oracle tests (★) in const_prop/const_fold/known_bits/setif are the most likely to +surface real bugs in this phase; prioritize those within each agent. diff --git a/docs/plan_optimizer_test_coverage.md b/docs/plan_optimizer_test_coverage.md new file mode 100644 index 00000000..74c15ab9 --- /dev/null +++ b/docs/plan_optimizer_test_coverage.md @@ -0,0 +1,168 @@ +# Plan: Comprehensive optimizer + codegen test coverage + +> Companion to `plan_binary_size_reduction.md`. This is the **test layer that gates +> Phase 4** (legacy→SSA optimizer consolidation) of that plan and regression-locks +> the Phase 1–3 codegen wins. + +## Context + +The path to ~1 MB in `plan_binary_size_reduction.md` depends on **Phase 4 — merging the +legacy linear-IR optimizer (`ir/opt_*.c`) into the SSA optimizer and deleting subsumed +passes** (~200–300 KB, "the 1 MB-maker"). In a fork with a documented history of subtle, +pass-local miscompiles, deleting/rewriting passes is only safe with strong per-pass tests. + +Today the optimizer is validated almost entirely **end-to-end**: the `tests/ir_tests/*.expect` +QEMU tests and the `tests/smoke/tcc_suite_test.py` gcc-torture suite. That catches *many* +miscompiles but **corner cases slip through** — the bug history is full of pass-local +defects that only surfaced as device HardFaults: known-bits load-width byte-drop, literal-pool +cross-placement, struct-by-value 9-byte packed operand, wide-string-literal merge, missing +`is_lval` guards in cmp-fold, LICM negative loop target, `ssa_opt_branch` `instr_to_block` +bounds. There is currently **zero isolated coverage of any optimization pass** and **no +coverage of backend instruction selection/emission** (`tests/unit/`'s `thop_*` suites cover +encoders only, not codegen). + +**Goal:** a host-side (seconds, no QEMU) test layer covering *every* pipeline-registered pass +and the codegen size levers, with a CI gate so the optimizer merge cannot silently drop +coverage and corner-case regressions are caught per-commit instead of per-device-boot. + +Decisions: +- **Hybrid mechanism** (effort split across three harnesses, below). +- **Hard CI gate on all registered passes** as the end-state acceptance criterion: the + fan-out drives coverage to 100% of pipeline-registered passes, then CI fails on *any* + uncovered registered pass — every new/merged pass must ship with a test. + +## Strategy: three complementary harnesses + +| Surface | Primary mechanism | Why | +|---|---|---| +| Legacy linear passes (`ir/opt_*.c`) | **Isolated `ut.h` unit tests** with hand-built IR | Surgical control over adversarial IR the C frontend can't emit; microsecond, deterministic; this is exactly where smoke misses and where merge risk concentrates | +| SSA passes (`ir/opt/ssa_opt_*.c`) | **Golden-IR snapshots** via `-dump-ir-passes` (host, no QEMU) | Hand-building a valid CFG+SSA per test is impractical; snapshotting the real pipeline after a named pass fits | +| Backend codegen / size levers | **objdump mnemonic pattern + count/threshold tests** (host, no QEMU) | cbz/cbnz fusion, `b.w`→`b.n`, R9 spill elim, struct byte handling are emission-level; counting mnemonics ties tests directly to the byte-size goal and locks in Phase 1–3 wins | + +A **coverage ledger** (machine-checkable) unifies the three and drives the CI gate. + +### Verified feasibility facts +- Every pass is `int tcc_ir_opt_(TCCIRState *ir)` — returns a change count, mutates IR in + place. Bare `(ir)` entry points are self-contained (they build whatever DU/loop info they + need internally — that's why the cascades in `ir/opt_pipeline.c:223-302` call them with just + `ir`). Passes exposed only as `_ex(IROptCtx*)` take an `IROptCtx` (`tcc_ir_opt_ctx_init`, + `ir/opt_engine.c`) whose require-helpers lazily build DU/blocks/loops. +- IR is hand-buildable: operand constructors `irop_make_vreg/imm32/symref/stackoff` + (`tccir_operand.h:393-507`), accessors/setters `tcc_ir_op_get_*` / `tcc_ir_op_set_*` + (`tccir.h:705-854`). **Do not** build via `tcc_ir_put` (`ir/core.c`) — frontend-coupled + (`SValue*`, auto-coalesce, `file->line_num`). Follow the minimal-`TCCIRState` pattern already + used by `tests/unit/arm/armv8m/test_ir_vreg.c` / `test_ir_pool.c` (README Pattern B/C). +- The **real IR dumper is `tcc_ir_show`** (`ir/dump.c:1069`); `tcc_ir_dump` (`ir/dump.c:196`) + is a dead stub. Output is **deterministic / snapshot-safe**: index + op name + `V/T/P`, + `#imm`, `GlobalSym()`, `StackLoc[..]`, `JMP to ` — no pointers/addresses/hashes. + ANSI spill coloring is gated behind `show_physical_regs`, forced to 0 by `dump_ir_after_pass` + (`tccgen.c:29030`). +- `-dump-ir` / `-dump-ir-passes=name[,...]` (or `all`) print `=== AFTER ===` blocks via + `dump_ir_after_pass()` / the `RUN_PASS()` macro — **but all `#ifdef CONFIG_TCC_DEBUG`** + (`Makefile:51-53`, enabled by `./configure --debug`). The shipped release `bin/armv8m-tcc` + prints nothing; the golden runner needs a debug-enabled **host** build. +- `arm-none-eabi-objdump` is available for the codegen tests. +- Pass count: ~137 `tcc_ir_opt_*` entry points (~68 unique after stripping `_ex`); the + authoritative "must cover" set is the pipeline-**registered** passes (the `PASS` / `PASS_GATED` + string-literal names in `ir/opt_pipeline.c` + the SSA pass tables). + +## Phases + +### Phase A — Harness foundation +- **`tests/unit/arm/armv8m/ir_build.{h,c}`** (new): test-only IR builder. `ut_ir_new/free` + (minimal zeroed `TCCIRState`, init only touched fields + live-interval arrays, reuse + `ut_init_intervals` from `test_ir_vreg.c`); `ut_emit(ir, op, dest, src1, src2)` appends an + `IRQuadCompact` and pushes present operands (per `irop_config[op].has_*`) into + `iroperand_pool` matching the `tcc_ir_op_get_*` layout; wrappers `ut_vreg/ut_imm/ + ut_jump_target` + flag setters (`is_lval`, `is_jump_target`); assertion helpers `ut_op/ + ut_dest/ut_is_nop` and `ut_snapshot(ir, buf)` (capture `tcc_ir_show` for sequence asserts). + ~150 lines, reused by every legacy-pass suite. +- **`tests/unit/ut.h`** (modify): add `UT_ASSERT_STREQ` and a no-op `UT_COVERS("")` + annotation macro the ledger script greps for. +- **`tests/unit/arm/armv8m/Makefile`** (modify): add `ir_build.c` to `UT_LOCAL_SRCS`; extend + `UT_MODULE_SRCS` with opt TUs under test + pure-IR deps (`ir/opt_engine.c`, `ir/cfg.c`, + `ir/licm.c`, selectively `ir/core.c`). Resolve link gaps via the stub-priority list in + `tests/unit/README.md` (extend `stubs.c` / `tcc_state_stub.c`). +- **`Makefile`** (modify): add a `tcc-debug-host` target (host `tcc` with `-DCONFIG_TCC_DEBUG`) + for the golden runner; add a `test-opt` aggregate target (unit suites + golden + codegen + pytest + ledger check). + +### Phase B — Tier-1 isolated-unit suites (legacy hot spots; open each with the known bug) +New `UT_SUITE` files in `tests/unit/arm/armv8m/`, each starting with the exact historical +miscompile as a regression test, then broadening; register each in `test_main.c`: +- `test_opt_knownbits.c` — load-width (1/2/4-byte) preservation, sign-vs-zero extend, masks. +- `test_opt_constfold.c` — IMM fold into CMP/arith, literal-pool placement, 32-bit wrap, LLONG/INT. +- `test_opt_constprop.c` — single-def prop; `addrtaken`-clear prologue (`opt_pipeline.c:318-325`). +- `test_opt_copyprop.c` — `is_lval`/DEREF preservation (`opt_copyprop.c:210-293`). +- `test_opt_cmpfold.c` — `cmp_expr_fold` / `cmp_const_offset_fold` / `cmp_field_fuse` `is_lval` guards. +- `test_opt_licm.c` — invariant only hoisted to a real preheader, never a negative/own-loop index. + +### Phase C — Golden-IR snapshot harness (SSA primary + whole-pipeline) +- **`tests/ir_tests/golden//.c` + `.expected`** (new) and runner + **`tests/ir_tests/test_golden_ir.py`**: run `tcc-debug-host -dump-ir-passes= -c case.c`, + extract the `=== AFTER ===` block, diff against `.expected`; `--update` regenerates. +- Primary mechanism for SSA passes: `ssa_opt_branch` (the `instr_to_block` bug), `ssa_opt_fold`, + `ssa_opt_sccp`, `ssa_opt_cprop`, `ssa_opt_gvn`, `ssa_opt_load_cse`, `ssa_opt_narrow`. + +### Phase D — Codegen disassembly tests (size levers) +- **`tests/ir_tests/test_codegen_asm.py`** (new): cross-compile `-c` (no link/boot), `objdump -d`, + assert (a) mnemonic presence/absence + counts, (b) per-function instruction/byte thresholds. + Targets mirror `plan_binary_size_reduction.md` Phases 1–2: R9 GOT-base spill elimination, + `b.w`→`b.n` narrowing, cbz/cbnz fusion, plus struct by-value 9-byte packed operand and + wide-string-literal merge. Reuse the cross-compile invocation from `tests/ir_tests/qemu_run.py`, + stopping before QEMU. Counting beats full goldens (robust to scheduling churn); keep full-disasm + goldens only for the trickiest sequences. + +### Phase E — Coverage ledger + CI gate +- **`tests/unit/check_pass_coverage.py`** (new): enumerate registered passes from the + `PASS`/`PASS_GATED` string-literal names in `ir/opt_pipeline.c` + the SSA pass tables; collect + tested passes from `UT_COVERS(...)` markers + `tests/ir_tests/golden//` dirs; diff and + report gaps. **`tests/unit/PASS_COVERAGE.md`** (new): checked-in ledger (pass → group → + test file(s) → kind → risk tier). +- Wire into CI alongside `make ut` (already `0 failed`-gated) via `make test-opt`. Gate policy: + during fan-out the script reports gaps non-fatally; once Phase F reaches 100% of registered + passes it flips to **hard fail on any uncovered registered pass** (the agreed end state). + +### Phase F — Fan out to all registered passes + merge-equivalence harness +- One suite/golden per remaining registered pass until the ledger is 100% (then flip the gate). +- **Legacy↔SSA equivalence harness** (the direct Phase-4 de-risker): for each legacy pass the + merge will subsume, snapshot its input→output on a corpus of small `.c` inputs; after the pass + is subsumed in SSA, diff old-path vs new-path `-dump-ir` for behavioral equivalence. Turns the + risky merge into a green/red signal. + +## Risk-prioritized first batch +Order = (historical-miscompile evidence) × (Phase-4 merge centrality) × (ease of isolated test): +1. `opt_knownbits` 2. `opt_constfold` 3. `opt_constprop` 4. `opt_copyprop` 5. cmp-fold family +6. `licm` — all Tier 1, reachable via bare `tcc_ir_opt_(ir)`. Then Tier 2 SSA analogues +(`ssa_opt_fold/sccp/cprop/gvn/load_cse/narrow/branch`) via golden-IR. Then Tier 3 codegen levers. + +## Sequencing vs `plan_binary_size_reduction.md` +- **Phases 1–3 (low-risk size levers) proceed in parallel** — each cbz/narrow-branch/R9 win + lands behind a Phase-D codegen test asserting the instruction-count drop, so the win is + regression-locked. +- **Phase 4 (the optimizer merge) is gated**: it does not start until Phase B/C coverage of the + passes it touches + the Phase-F equivalence harness exist. Phase 4's per-pass verification + ("disable → smoke+torture → delete") gains a fast pre-check: the equivalence harness must be + green before the slow QEMU gate runs. + +## Verification +- `make ut` — all unit suites pass, `0 failed`; each Tier-1 suite **fails first** if its target + fix is reverted (proves it bites). +- `make test-opt` — golden-IR + codegen pytest modules pass; `--update` regenerates goldens. +- `python tests/unit/check_pass_coverage.py` — prints the gap list; after Phase F exits non-zero + on any uncovered registered pass. +- Determinism spot-check: run a golden case twice, confirm byte-identical `=== AFTER ===`. +- No regression of the existing slow path: full `tests/smoke/tcc_suite_test.py` / + `tests/ir_tests/test_qemu.py` still pass. + +## Files +- **New:** `tests/unit/arm/armv8m/ir_build.{h,c}`, + `tests/unit/arm/armv8m/test_opt_{knownbits,constfold,constprop,copyprop,cmpfold,licm}.c`; + `tests/ir_tests/test_golden_ir.py`, `tests/ir_tests/golden/`; `tests/ir_tests/test_codegen_asm.py`; + `tests/unit/check_pass_coverage.py`, `tests/unit/PASS_COVERAGE.md`. +- **Modify:** `tests/unit/ut.h`, `tests/unit/arm/armv8m/Makefile`, `tests/unit/arm/armv8m/test_main.c`, + `tests/unit/arm/armv8m/{stubs.c,tcc_state_stub.c}` (as link gaps surface), `Makefile`. +- **Reuse (read, don't reinvent):** `tccir_operand.h` (`irop_make_*`), `tccir.h` + (`tcc_ir_op_get/set_*`), `ir/dump.c` (`tcc_ir_show`), `ir/opt_pipeline.c` (registered-pass + names), `ir/opt_engine.c` (`tcc_ir_opt_ctx_*`), `tests/ir_tests/qemu_run.py` (cross-compile + path), `tests/unit/README.md` (suite-authoring + stub priority). diff --git a/ir/opt_loop_utils.c b/ir/opt_loop_utils.c index 29637364..3cac3b8d 100644 --- a/ir/opt_loop_utils.c +++ b/ir/opt_loop_utils.c @@ -808,7 +808,14 @@ int insert_instr_at(TCCIRState *ir, int pos, TccIrOp op, IROperand dest, IROpera /* Create the new instruction using operand pool */ IRQuadCompact *new_q = &ir->compact_instructions[pos]; new_q->op = op; - new_q->orig_index = pos; + /* Assign a fresh unique orig_index — never re-use the compact position + * `pos`, which both collides with an existing instruction's key and is not + * reflected in ir->max_orig_index. Side tables keyed by orig_index and + * sized max_orig_index+1 (ir->barrel_shifts[], shift64_dead_half[], + * bfi_params[], the codegen orig->code map) would otherwise be + * under-allocated and over-read in codegen. Bumping max_orig_index keeps + * them sized to cover every live orig_index. */ + new_q->orig_index = ++ir->max_orig_index; new_q->is_jump_target = 0; /* shifted instructions carry their flag; new slot has none */ new_q->no_unroll = 0; new_q->line_num = 0; diff --git a/ir/ssa.c b/ir/ssa.c index 264ea011..d633016d 100644 --- a/ir/ssa.c +++ b/ir/ssa.c @@ -149,21 +149,49 @@ static void ssa_var_info_free(SSAVarInfo *info) tcc_free(info->var_btype); } -static uint8_t *ssa_build_promotable(const SSAVarInfo *info, int nb, int *out_count) +/* Decide whether a local VAR should be promoted to SSA (and get phi nodes). + * + * Single-block CFG: no back-edges, so any non-addrtaken VAR is safely + * promotable to a TEMP via straight-line renaming — no phi placement needed. + * Enabling this lets GVN / cprop / DCE see local-variable defs in leaf + * functions. + * + * Multi-block CFG: a VAR defined in >=2 blocks (multi_block_def) needs phis and + * is promoted. A VAR defined in only ONE block ALSO needs a phi when that def + * does not dominate all later uses — i.e. its def-block has a non-empty + * dominance frontier. The classic case is a value defined only inside a loop + * and read again on the next iteration through the back-edge (the loop header + * is in the def-block's DF): without a phi it stays an unpromoted VAR with no + * loop-header definition, and the register allocator can hand it a register + * that is clobbered around the loop body (gcc-torture pr125291). A value + * defined on one arm of a branch and read after the merge is the same shape. + * Promoting it is always safe: the phi resolver drops undef (vreg<0) operands, + * so a path that leaves the var genuinely uninitialized is unchanged. */ +static int ssa_var_promotable(const SSAVarInfo *info, IRCFG *cfg, int nb, int v, + int single_block) +{ + if (bitset_test(info->addrtaken, v)) + return 0; + if (single_block || bitset_test(info->multi_block_def, v)) + return 1; + /* Single-block-def: promote iff a phi would actually be placed, i.e. some + * def-block has a non-empty dominance frontier. */ + const uint8_t *def_bits = &info->def_blocks[v * info->block_bitset_bytes]; + for (int b = 0; b < nb; b++) { + if (bitset_test(def_bits, b) && cfg->blocks[b].num_df > 0) + return 1; + } + return 0; +} + +static uint8_t *ssa_build_promotable(const SSAVarInfo *info, IRCFG *cfg, int nb, + int *out_count) { int num_vars = info->num_vars; - /* Single-block CFG: no back-edges, so any non-addrtaken VAR is safely - * promotable to a TEMP via straight-line renaming — no phi placement - * needed. Enabling this lets GVN / cprop / DCE see local-variable defs - * in leaf functions. Multi-block CFGs must keep the multi_block_def - * criterion: a VAR defined in only one block but used across a back-edge - * still needs a phi at the loop header. */ int single_block = (nb <= 1); int count = 0; for (int v = 0; v < num_vars; v++) { - if (bitset_test(info->addrtaken, v)) - continue; - if (single_block || bitset_test(info->multi_block_def, v)) + if (ssa_var_promotable(info, cfg, nb, v, single_block)) count++; } *out_count = count; @@ -172,9 +200,7 @@ static uint8_t *ssa_build_promotable(const SSAVarInfo *info, int nb, int *out_co uint8_t *is_promotable = tcc_mallocz((num_vars + 7) / 8); for (int v = 0; v < num_vars; v++) { - if (bitset_test(info->addrtaken, v)) - continue; - if (single_block || bitset_test(info->multi_block_def, v)) + if (ssa_var_promotable(info, cfg, nb, v, single_block)) bitset_set(is_promotable, v); } return is_promotable; @@ -255,7 +281,7 @@ IRSSAState *tcc_ir_ssa_construct(TCCIRState *ir, IRCFG *cfg) ssa_scan_var_defs(ir, cfg, &info); int promotable_count; - uint8_t *is_promotable = ssa_build_promotable(&info, nb, &promotable_count); + uint8_t *is_promotable = ssa_build_promotable(&info, cfg, nb, &promotable_count); if (!is_promotable) { ssa_var_info_free(&info); return NULL; @@ -274,7 +300,11 @@ IRSSAState *tcc_ir_ssa_construct(TCCIRState *ir, IRCFG *cfg) int phi_counter = 0; for (int v = 0; v < num_vars; v++) { - if (!bitset_test(info.multi_block_def, v) || bitset_test(info.addrtaken, v)) + /* Place phis for every promoted var (is_promotable already excludes + * addrtaken). For single-block-def vars this now also covers the ones kept + * as VARs before — loop-carried / branch-merge-live values that need a phi. + * In a single-block CFG the def-block has an empty DF, so this places none. */ + if (!bitset_test(is_promotable, v)) continue; uint8_t *def_bits = &info.def_blocks[v * bitset_bytes]; phi_counter = ssa_place_phis_for_var(ssa, ir, cfg, v, info.var_btype[v], def_bits, diff --git a/tccgen.c b/tccgen.c index 281359d7..178df89e 100644 --- a/tccgen.c +++ b/tccgen.c @@ -4065,6 +4065,29 @@ static void gen_opl(int op) /* FALLTHROUGH */ case '*': t = vtop->type.t; /* Save type for lbuild at end */ + /* Speculative / code-suppressed contexts (try_inline_const_eval, if(0) + * dead branches, constant-expression and data-only evaluation) run with + * nocode_wanted set, where tcc_ir_put is a no-op (see ir/core.c) and gv() + * is suppressed. The generic 64x64 lexpand/lbuild expansion below assumes + * real register codegen and walks vtop off the vstack into the heap in + * that state. No code is emitted here, so just collapse the two operands + * into a single 64-bit result, mirroring the +/-/&/|/^ IR paths above. + * (CODE_OFF_BIT-only dead code after return still needs real IR for + * backpatching, so exclude it — same predicate tcc_ir_put uses.) */ + if (nocode_wanted & ~CODE_OFF_BIT) + { + vtop--; + vtop->type.t = VT_LLONG | (t & VT_UNSIGNED); + vtop->r = 0; + if (tcc_state->ir) + { + vtop->vr = tcc_ir_get_vreg_temp(tcc_state->ir); + tcc_ir_set_llong_type(tcc_state->ir, vtop->vr); + } + else + vtop->vr = -1; + break; + } /* Widening-multiply peephole: when both 64-bit operands are 32->64 * extensions (zero or sign), emit a single 32x32->64 UMULL/SMULL * instead of the generic 64x64 expansion. */ diff --git a/tests/gcctestsuite/conftest.py b/tests/gcctestsuite/conftest.py index 2cec570e..636fcdf0 100644 --- a/tests/gcctestsuite/conftest.py +++ b/tests/gcctestsuite/conftest.py @@ -88,12 +88,6 @@ def get_opt_levels(env_var: str = "YASOS_TCC_TEST_OPT_LEVELS", *, default: tuple # builtins/ tests — builtin override tests requiring lib/main.c framework # compile/ tests — compilation failures (parser, type system, unsupported features) # always_inline related failures (need proper fix for inline expansion) - # Confirmed real miscompile (not an unsupported feature): the function - # computes the wrong result at every -O level (xfail rather than skip so a - # future codegen fix shows up as an XPASS). Minimal repro: a while loop with - # `(short)` truncation, an unsigned-char shift count (`flagbyte >> flagbits`) - # and `& 3`; tcc returns 3 at -O0 and 2 at -O1/-O2 instead of 1. - "pr125291", } # GCC Torture tests expected to fail only at -O1 diff --git a/tests/unit/PASS_COVERAGE.md b/tests/unit/PASS_COVERAGE.md new file mode 100644 index 00000000..fba5a9dc --- /dev/null +++ b/tests/unit/PASS_COVERAGE.md @@ -0,0 +1,121 @@ +# Optimizer + codegen test-coverage tracker + +Progress tracker for the per-pass / codegen unit-test effort described in +`docs/plan_optimizer_test_coverage.md`. This file is the source of truth for +"what is covered" until `check_pass_coverage.py` (Phase E) automates the diff. + +**Working rules** (per user, 2026-06-26): +- Write tests in parallel to the bug-fixing work. **Do NOT change production code.** +- If a test surfaces a bug, do **not** fix it here — record it under *Findings* below + (with a minimal repro) and leave the test as a documented expectation. +- Each suite annotates the pass it covers with `UT_COVERS("")` so the future + ledger script can enumerate coverage automatically. + +Legend: `[x]` done · `[~]` written+verified-in-isolation, NOT yet registered in build · `[ ]` todo · `[!]` blocked / bug found + +--- + +## STATUS SNAPSHOT (2026-06-26) + +- **11 suites, 69 tests** written this session. **All 11 suites are now integrated** and run in `make ut` (**589 tests, 0 failed**). +- Harness foundation (Phase A) complete. Shared base modules already wired into the Makefile: `ir/opt.c`, `ir/opt_alias.c`, `ir/cfg.c` + `get_tok_str`, `elfsym`, and frontend symbol-table stubs in `stubs.c`. +- **No production bugs found** by any suite — all asserts pin current (correct) behavior. These are regression/characterization guards for the upcoming legacy→SSA optimizer merge. + +The session-scratch self-verify harness (`verify_suite.sh` + `utbase/`) was temporary and is no longer present; the integrated `make ut` build is the source of truth. + +--- + +## Phase A — Harness foundation +- [x] `ir_build.h` — hand-built IR builder (`utb_new/emit/temp/imm/...`) for isolated pass tests +- [x] `ut.h` — `UT_COVERS("")` annotation macro +- [x] Makefile — link opt passes via `--gc-sections` (isolates `irop_config` from heavy `core.c`) +- [x] Shared base modules wired: `ir/opt.c` (pass timing + `tcc_ir_find_defining_instruction`), `ir/opt_alias.c` (`ir_opt_store_btype_size_bytes`), `ir/cfg.c` (dominators), `get_tok_str` stub +- [ ] `UT_ASSERT_STREQ` in `ut.h` (only needed once golden/snapshot asserts land) + +### How the isolated harness links (for future suites) +A pass `int tcc_ir_opt_(TCCIRState*)` links against: its own TU + the prebuilt base +(`core.c` for `irop_config`, `opt_utils.c`, `opt.c`, `opt_alias.c`, `cfg.c`, `tccir_operand.c`, +`pool/type/vreg`, stubs). `-ffunction-sections -fdata-sections` + `-Wl,--gc-sections` GC core.c's +unreferenced frontend functions, so per-pass module deps stay tiny. Build/run: `make ut`. + +--- + +## Phase B — Tier-1 legacy passes +| Suite | File | Pass(es) covered | Tests | Extra module srcs to add | Status | +|---|---|---|---|---|---| +| opt_neg_chain | test_opt_neg_chain.c | neg_chain_cse | 4 | ir/opt_neg_chain.c | **[x] integrated** | +| opt_knownbits | test_opt_knownbits.c | known_bits | 7 | ir/opt_knownbits.c | **[x] integrated** | +| opt_copyprop | test_opt_copyprop.c | copy_prop | 9 | ir/opt_copyprop.c | **[x] integrated** | +| opt_cmp_fuse | test_opt_cmp_fuse.c | cmp_field_fuse | 5 | ir/opt_cmp_fuse.c | **[x] integrated** | +| opt_cmpfold | test_opt_cmpfold.c | cmp_expr_fold, cmp_const_offset_fold, cmp_field_fuse | 5 | ir/opt_constprop.c, ir/opt_du.c, ir/opt_cmp_fuse.c, ir/opt_dce.c + `elfsym` stub | **[x] integrated** | +| opt_constprop | test_opt_constprop.c | const_var_prop, const_prop | 11 | ir/opt_constprop.c, ir/opt_du.c | **[x] integrated** | +| opt_constfold | test_opt_constfold.c | self_copy_elim, float_narrowing | 6 | ir/opt_constfold.c (frontend stubs moved to `stubs.c`) | **[x] integrated** (see Finding #1) | +| opt_licm | test_opt_licm.c | licm | 4 | ir/licm.c | **[x] integrated** (real hoist positive) | +| opt_jump_thread | test_opt_jump_thread.c | jump_threading, eliminate_fallthrough | 8 | ir/opt_jump_thread.c | **[x] integrated** | +| opt_setif_or_taut | test_opt_setif_or_taut.c | setif_or_tautology | 5 | ir/opt_setif_or_taut.c | **[x] integrated** | +| opt_dead_lea_store | test_opt_dead_lea_store.c | dead_lea_store_elim | 5 | ir/opt_dead_lea_store.c | **[x] integrated** | + +### >>> Integration complete <<< +All 10 verified suites are registered in `stubs.c`, the Makefile (`UT_MODULE_SRCS` / `UT_LOCAL_SRCS`), and `test_main.c`. `make ut` reports **589 tests, 0 failed**. + +Notes from the combined link: +- The 4 frontend link stubs originally inside `test_opt_constfold.c` (`global_stack`, `sym_push2`, `external_global_sym`, `tok_alloc_const`) were moved to `stubs.c` so the union link has a single definition. +- The `elfsym` stub was added to `stubs.c` for `ir/opt_dce.c` (needed by the cmpfold suite). + +--- + +## Phase B2 — Corner-case unit tests — NEXT (user priority, before bug-hunting tracks) +See `docs/plan_corner_case_tests.md`. Drive each of the 11 passes into its edge cases (boundaries, +overflow/UB-shaped inputs, widths/signedness, degenerate IR, control-flow/lval/memory corners, +idempotence, ASAN robustness). Arithmetic ★ cases assert independently-computed values, so they can +*find* bugs, not just characterize. +- [ ] §B harness extensions first (serial): `utb_emit4`, symref/stackoff/flag helpers, fixpoint helper, **settable `get_tok_str` table** (resolves Finding #1) +- [ ] Per-pass corner-case fan-out (parallel, one agent per `test_opt_*.c`) +- [ ] ASAN run of the unit binary over the new tests + +## Phase C — Tier-2 SSA passes (golden-IR snapshots, host, no QEMU) — TODO +- [ ] `ssa_opt_branch` (`instr_to_block` bounds), `ssa_opt_fold`, `ssa_opt_sccp`, `ssa_opt_cprop`, `ssa_opt_gvn`, `ssa_opt_load_cse`, `ssa_opt_narrow` + +## Phase D — Tier-3 codegen size levers (objdump pattern/count, host) — TODO +- [ ] R9 GOT-base spill elimination; `b.w`→`b.n` narrowing; cbz/cbnz fusion; struct by-value 9-byte packed operand; wide-string-literal merge + +## Phase BH — Real bug hunting (independent oracles) — PLANNED, do before Phase F +See `docs/plan_bug_hunting.md`. Characterization tests (Phase B) don't *find* bugs; these do, via +independent oracles. Recommended order: +- [ ] Track 1 — ASAN/UBSan corpus sweep (memory-safety class; proven, ~1d) +- [ ] Track 2 — O-level self-consistency differential (miscompile class; ~2-3d) +- [ ] Track 4 — IR metamorphic / semantics-preservation fuzzer (per-pass, host, localizing; flagship — also the substrate for Phase F) +- [ ] Track 3 — differential vs arm-none-eabi-gcc (wrong-at-all-levels class; ~2-3d) + +## Phase E — Ledger + CI gate — TODO +- [ ] `check_pass_coverage.py` — enumerate `PASS`/`PASS_GATED` in `ir/opt_pipeline.c` vs `UT_COVERS` markers; wire into CI (soft-fail first) + +## Phase F — Remaining registered passes + legacy↔SSA equivalence harness — TODO +Many multi-pass files only partially covered. Still uncovered entries include: +- opt_copyprop.c: `cse_global_load`, `globalsym_cse`, `cse_param_add`, `local_load_cse`, `local_alu_cse`, `bool_cse` +- opt_constprop.c: `global_init_prop`, `symref_const_prop`, `complex_const_param_fold`, `value_tracking` +- opt_constfold.c: `const_string_calls`, `const_call_replace`, `switch_call_replace`, `param_addrof_const_fold`, `local_addrof_const_fold` (these pull frontend symbols — need stubs/harness work) +- opt_jump_thread.c covered; remaining small passes: opt_loop_dead, opt_reroll, opt_bitfield, opt_const_aggregate, opt_dead_vla, opt_switch_data (deferred), opt_gens_*, opt_hash, opt_xform, opt_engine, opt_setif_or_taut covered, ... +- [ ] Equivalence harness (old legacy path vs new SSA path on a `.c` corpus) + +--- + +## Findings (DO NOT fix here — hand off to bug-fix work) + +1. **Harness limitation (not a pass bug): name-gated passes can't exercise their positive fold.** + `self_copy_elim` and `float_narrowing` (opt_constfold.c) decide solely on the callee name from + `get_tok_str(callee->v)` (e.g. needs "memcpy" / "__aeabi_f2d"). The base `get_tok_str` stub returns + a constant `"?"`, so the fold is structurally unreachable — these suites only assert the pass correctly + *declines* (non-vacuous guard tests). To test the real fold, give the harness a settable token-name + table (a `get_tok_str` that reads a test-populated map) or real token state. Same blocker for the + `*addrof_const_fold` / `*_string_calls` / `*_call_replace` constfold passes (Phase F). + +2. **No production bugs found.** All 9 agent suites + cmpfold assert current behavior and pass, including + the Tier-1 historical bug-class guards (copyprop `is_lval`/DEREF preservation; cmp_fuse `is_lval` base + guard; knownbits narrow-load mask/sign-extend; licm hoist-only-to-dominating-preheader; jump-thread + backward-edge guard). These now act as regression guards for the legacy→SSA optimizer merge. + +## Deferred +- **opt_switch_data** (`switch_to_data`, `switch_collapse`): needs ELF/section + frontend state + (`get_sym_ref`, `greloc`, `int_type`, `section_add`) — not a clean IR-only unit test. Revisit with a + section/codegen stub layer or move to an integration-level test. diff --git a/tests/unit/arm/armv8m/Makefile b/tests/unit/arm/armv8m/Makefile index 9ce30b7b..6feeb254 100644 --- a/tests/unit/arm/armv8m/Makefile +++ b/tests/unit/arm/armv8m/Makefile @@ -28,8 +28,12 @@ UT_DEFINES := \ -DTCC_TARGET_ARM_THUMB \ -DTCC_TARGET_ARM_ARCHV8M +# -ffunction-sections/-fdata-sections + -Wl,--gc-sections (link rule below) let +# us pull the irop_config[] table out of the heavy ir/core.c without dragging in +# its frontend functions (sym_push, vtop, ...) — unreferenced sections are GC'd. UT_CFLAGS := -std=c11 -g -O0 -Wall -Werror -Wno-unused-function \ -Wno-declaration-after-statement \ + -ffunction-sections -fdata-sections \ -I$(TOP) -I$(TOP)/ir -I$(UT_ROOT) $(UT_DEFINES) UT_DEPFLAGS := -MMD -MP @@ -65,7 +69,25 @@ UT_MODULE_SRCS := \ $(TOP)/arch/arm/thumb/thop_mul.c \ $(TOP)/arch/arm/thumb/thop_mvn.c \ $(TOP)/arch/arm/thumb/thop_pld.c \ - $(TOP)/arch/arm/thumb/thop_rev.c + $(TOP)/arch/arm/thumb/thop_rev.c \ + $(TOP)/tccir_operand.c \ + $(TOP)/ir/core.c \ + $(TOP)/ir/opt_utils.c \ + $(TOP)/ir/opt_neg_chain.c \ + $(TOP)/ir/opt_knownbits.c \ + $(TOP)/ir/opt_copyprop.c \ + $(TOP)/ir/opt_cmp_fuse.c \ + $(TOP)/ir/opt_constprop.c \ + $(TOP)/ir/opt_du.c \ + $(TOP)/ir/opt_constfold.c \ + $(TOP)/ir/licm.c \ + $(TOP)/ir/opt_jump_thread.c \ + $(TOP)/ir/opt_setif_or_taut.c \ + $(TOP)/ir/opt_dead_lea_store.c \ + $(TOP)/ir/opt_dce.c \ + $(TOP)/ir/opt.c \ + $(TOP)/ir/opt_alias.c \ + $(TOP)/ir/cfg.c UT_MODULE_OBJS := $(patsubst $(TOP)/%.c,$(BUILD_DIR)/%.o,$(UT_MODULE_SRCS)) @@ -83,6 +105,17 @@ UT_LOCAL_SRCS := \ test_ir_pool.c \ test_ir_type.c \ test_ir_vreg.c \ + test_opt_neg_chain.c \ + test_opt_knownbits.c \ + test_opt_copyprop.c \ + test_opt_cmp_fuse.c \ + test_opt_cmpfold.c \ + test_opt_constprop.c \ + test_opt_constfold.c \ + test_opt_licm.c \ + test_opt_jump_thread.c \ + test_opt_setif_or_taut.c \ + test_opt_dead_lea_store.c \ test_thop_adr.c \ test_thop_alu_reg.c \ test_thop_block.c \ @@ -119,7 +152,7 @@ run: $(UT_BIN) $(UT_BIN): $(UT_OBJS) @mkdir -p $(dir $@) - $(HOSTCC) -o $@ $^ + $(HOSTCC) -Wl,--gc-sections -o $@ $^ # Local source files → build/*.o $(BUILD_DIR)/%.o: %.c $(UT_ROOT)/ut.h Makefile @@ -136,6 +169,11 @@ $(BUILD_DIR)/libtcc.o: $(TOP)/libtcc.c Makefile @mkdir -p $(dir $@) $(HOSTCC) $(UT_CFLAGS) $(UT_DEPFLAGS) -c $< -o $@ +# tccir_operand.o — top-level source (pool getters for the opt-pass suites). +$(BUILD_DIR)/tccir_operand.o: $(TOP)/tccir_operand.c Makefile + @mkdir -p $(dir $@) + $(HOSTCC) $(UT_CFLAGS) $(UT_DEPFLAGS) -c $< -o $@ + # arch/arm/arm.o — build from the tinycc source tree. $(BUILD_DIR)/arch/arm/%.o: $(TOP)/arch/arm/%.c Makefile @mkdir -p $(dir $@) diff --git a/tests/unit/arm/armv8m/ir_build.h b/tests/unit/arm/armv8m/ir_build.h new file mode 100644 index 00000000..7a39a509 --- /dev/null +++ b/tests/unit/arm/armv8m/ir_build.h @@ -0,0 +1,105 @@ +/* + * ir_build.h - hand-built IR construction for isolated optimization-pass tests + * + * Optimization passes have a clean signature `int tcc_ir_opt_(TCCIRState*)` + * that mutates ir->compact_instructions[] / ir->iroperand_pool[] in place. This + * header lets a unit test build a tiny instruction sequence by hand, run one + * pass, and assert on the result — without the frontend-coupled tcc_ir_put() + * (which needs SValue/CType/file state) and without QEMU. + * + * Layout mirrors what the inline accessors in tccir.h expect: per instruction, + * operands are appended to iroperand_pool as [dest?, src1?, src2?] according to + * irop_config[op]. See tests/unit/README.md (Pattern B) and PASS_COVERAGE.md. + * + * Copyright (c) 2026 Mateusz Stadnik + * + * This library is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License. + */ + +#ifndef TCC_UT_IR_BUILD_H +#define TCC_UT_IR_BUILD_H + +#define USING_GLOBALS +#include "ir.h" + +/* Generous fixed pools — unit-test functions are tiny. */ +#define UTB_MAX_INSTR 256 +#define UTB_MAX_OPERANDS 1024 + +static inline TCCIRState *utb_new(void) +{ + TCCIRState *ir = (TCCIRState *)tcc_mallocz(sizeof(*ir)); + ir->compact_instructions = (IRQuadCompact *)tcc_mallocz(sizeof(IRQuadCompact) * UTB_MAX_INSTR); + ir->iroperand_pool = (IROperand *)tcc_mallocz(sizeof(IROperand) * UTB_MAX_OPERANDS); + ir->iroperand_pool_count = 0; + ir->next_instruction_index = 0; + return ir; +} + +static inline void utb_free(TCCIRState *ir) +{ + if (!ir) + return; + tcc_free(ir->compact_instructions); + tcc_free(ir->iroperand_pool); + tcc_free(ir); +} + +/* ---- operand constructors ---- */ + +static inline IROperand utb_temp(int pos, int btype) +{ + return irop_make_vreg(TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, pos), btype); +} + +static inline IROperand utb_var(int pos, int btype) +{ + return irop_make_vreg(TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_VAR, pos), btype); +} + +static inline IROperand utb_param(int pos, int btype) +{ + return irop_make_vreg(TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_PARAM, pos), btype); +} + +/* Immediate: vreg arg 0 -> vreg_type 0 -> irop_get_vreg() returns "no vreg", + * matching the production convention `irop_make_imm32(0, val, btype)`. */ +static inline IROperand utb_imm(int32_t val, int btype) +{ + return irop_make_imm32(0, val, btype); +} + +#define UTB_NONE IROP_NONE + +/* ---- instruction emission ---- */ + +/* Append one instruction; returns its index. Operands present per irop_config. */ +static inline int utb_emit(TCCIRState *ir, TccIrOp op, IROperand dest, IROperand src1, IROperand src2) +{ + int i = ir->next_instruction_index++; + IRQuadCompact *q = &ir->compact_instructions[i]; + q->orig_index = i; + q->op = op; + q->operand_base = (uint32_t)ir->iroperand_pool_count; + q->line_num = 0; + q->is_jump_target = 0; + q->no_unroll = 0; + if (irop_config[op].has_dest) + ir->iroperand_pool[ir->iroperand_pool_count++] = dest; + if (irop_config[op].has_src1) + ir->iroperand_pool[ir->iroperand_pool_count++] = src1; + if (irop_config[op].has_src2) + ir->iroperand_pool[ir->iroperand_pool_count++] = src2; + return i; +} + +/* ---- read-back accessors for assertions ---- */ + +static inline TccIrOp utb_op(TCCIRState *ir, int i) { return ir->compact_instructions[i].op; } +static inline IROperand utb_dest(TCCIRState *ir, int i) { return tcc_ir_op_get_dest(ir, &ir->compact_instructions[i]); } +static inline IROperand utb_src1(TCCIRState *ir, int i) { return tcc_ir_op_get_src1(ir, &ir->compact_instructions[i]); } +static inline IROperand utb_src2(TCCIRState *ir, int i) { return tcc_ir_op_get_src2(ir, &ir->compact_instructions[i]); } +static inline int utb_vreg(IROperand op) { return irop_get_vreg(op); } + +#endif /* TCC_UT_IR_BUILD_H */ diff --git a/tests/unit/arm/armv8m/stubs.c b/tests/unit/arm/armv8m/stubs.c index 945a3cc8..8dc2d5b4 100644 --- a/tests/unit/arm/armv8m/stubs.c +++ b/tests/unit/arm/armv8m/stubs.c @@ -101,3 +101,52 @@ int set_elf_sym(struct Section *s, addr_t value, unsigned long size, int info, i (void)name; return 0; } + +/* get_tok_str is declared `const char *get_tok_str(int, CValue*)` in tcc.h and + * used by some opt passes only for diagnostic/symbol naming. Unit tests never + * inspect the result, so return a constant. CValue is opaque here (no tcc.h), + * hence the void* parameter — the linker resolves by name regardless. */ +const char *get_tok_str(int v, void *cv) +{ + (void)v; + (void)cv; + return "?"; +} + +/* ───── Frontend link stubs pulled in by optimizer passes ───── + * + * opt_constfold.c/opt_utils.c reference the symbol-table helpers below. + * They are unreachable at runtime for hand-built IR tests, but --gc-sections + * keeps them reachable from pass entry points, so the linker needs a + * definition. Keep them opaque (no tcc.h) — pointer args/returns are enough. + */ +struct Sym; +struct CType; + +struct Sym *global_stack = NULL; + +struct Sym *sym_push2(struct Sym **ps, int v, int t, int c) +{ + (void)ps; (void)v; (void)t; (void)c; + return NULL; +} + +struct Sym *external_global_sym(int v, struct CType *type) +{ + (void)v; (void)type; + return NULL; +} + +int tok_alloc_const(const char *str) +{ + (void)str; + return 0; +} + +/* opt_dce.c (pulled in by the cmpfold suite) calls elfsym() on callee symbols. + * Hand-built IR has no real ELF symbols, so return NULL. */ +void *elfsym(void *s) +{ + (void)s; + return 0; +} diff --git a/tests/unit/arm/armv8m/test_main.c b/tests/unit/arm/armv8m/test_main.c index 95e3b7b0..baf7d2d0 100644 --- a/tests/unit/arm/armv8m/test_main.c +++ b/tests/unit/arm/armv8m/test_main.c @@ -13,6 +13,17 @@ UT_DECLARE_SUITE(chained_hash); UT_DECLARE_SUITE(ir_pool); UT_DECLARE_SUITE(ir_type); UT_DECLARE_SUITE(ir_vreg); +UT_DECLARE_SUITE(opt_neg_chain); +UT_DECLARE_SUITE(opt_knownbits); +UT_DECLARE_SUITE(opt_copyprop); +UT_DECLARE_SUITE(opt_cmp_fuse); +UT_DECLARE_SUITE(opt_cmpfold); +UT_DECLARE_SUITE(opt_constprop); +UT_DECLARE_SUITE(opt_constfold); +UT_DECLARE_SUITE(opt_licm); +UT_DECLARE_SUITE(opt_jump_thread); +UT_DECLARE_SUITE(opt_setif_or_taut); +UT_DECLARE_SUITE(opt_dead_lea_store); UT_DECLARE_SUITE(thop_adr); UT_DECLARE_SUITE(thop_alu_reg); UT_DECLARE_SUITE(thop_bitfield); @@ -47,6 +58,17 @@ int main(void) UT_RUN_SUITE(ir_pool); UT_RUN_SUITE(ir_type); UT_RUN_SUITE(ir_vreg); + UT_RUN_SUITE(opt_neg_chain); + UT_RUN_SUITE(opt_knownbits); + UT_RUN_SUITE(opt_copyprop); + UT_RUN_SUITE(opt_cmp_fuse); + UT_RUN_SUITE(opt_cmpfold); + UT_RUN_SUITE(opt_constprop); + UT_RUN_SUITE(opt_constfold); + UT_RUN_SUITE(opt_licm); + UT_RUN_SUITE(opt_jump_thread); + UT_RUN_SUITE(opt_setif_or_taut); + UT_RUN_SUITE(opt_dead_lea_store); UT_RUN_SUITE(thop_adr); UT_RUN_SUITE(thop_alu_reg); UT_RUN_SUITE(thop_bitfield); diff --git a/tests/unit/arm/armv8m/test_opt_cmp_fuse.c b/tests/unit/arm/armv8m/test_opt_cmp_fuse.c new file mode 100644 index 00000000..1277e469 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_cmp_fuse.c @@ -0,0 +1,260 @@ +/* + * test_opt_cmp_fuse.c - suite for ir/opt_cmp_fuse.c (aggregate field-compare + * fusion, tcc_ir_opt_cmp_field_fuse) + * + * The pass collapses the `a.f1 != b.f1 || a.f2 != b.f2 || ...` idiom — a run of + * >=2 bitfield-extract `!=`-compares that all branch to the same target — into a + * single masked word compare: + * + * CMP extract_i(A), extract_i(B) ; JUMPIF "!=" -> L (per field i) + * -> t = A XOR B ; t &= (union of field masks) ; CMP t,#0 ; JUMPIF "!=" -> L + * + * cmpf_trace() walks each CMP operand back through an AND/SHL+SHR/SHR extract + * chain to a base word + a 32-bit field mask. The two sides must agree on the + * mask (mA == mB), the run must share base words + branch target, and there + * must be >=2 units. cmpf_same_base() refuses to line two base words up when + * their `is_lval` flags differ (the Tier-1 lvalue/memory-deref guard): a value + * read directly from memory must not be fused with a register value. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_cmp_field_fuse(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 + +/* TOK_* condition codes the JUMPIF condition operand carries (see tcc.h). The + * pass only fuses `!=` (TOK_NE) branches. */ +#define UT_TOK_NE 0x95 +#define UT_TOK_EQ 0x94 + +/* The fused-target label encoded in every JUMPIF dest operand's imm. */ +#define LBL 99 + +/* ----------------------------------------------------------- helpers */ + +/* The positive path calls tcc_ir_get_vreg_temp() to allocate the XOR/AND result + * temps; give the IR a temp live-interval table so the allocator's bounds check + * passes without taking the realloc-from-zero branch. Positions [base..size) are + * available; the pass hands out the next two (base, base+1). */ +static void utb_alloc_temp_intervals(TCCIRState *ir, int base, int size) +{ + ir->temporary_variables_live_intervals = + (IRLiveInterval *)tcc_mallocz(sizeof(IRLiveInterval) * size); + ir->temporary_variables_live_intervals_size = size; + ir->next_temporary_variable = base; +} + +/* An AND-extract feeder: dest(TEMP pos) = AND src(P), #mask. Returns the + * instruction index. If src_is_lval, the (param) base word is flagged as a memory + * lvalue so cmpf_same_base() will treat it as a distinct base. */ +static int utb_emit_and_extract(TCCIRState *ir, int dest_pos, int src_param_pos, + int32_t mask, int src_is_lval) +{ + IROperand src = utb_param(src_param_pos, I32); + src.is_lval = src_is_lval ? 1 : 0; + return utb_emit(ir, TCCIR_OP_AND, utb_temp(dest_pos, I32), src, utb_imm(mask, I32)); +} + +/* ------------------------------------------------------ POSITIVE test */ + +/* Two field-compare units that branch to the same label fuse into XOR(+AND)+CMP: + * + * 0: T0 = AND P0, #0x00FF ; A.f1 + * 1: T1 = AND P1, #0x00FF ; B.f1 + * 2: CMP T0, T1 ; unit 1 (i) + * 3: JUMPIF != -> L99 + * 4: T2 = AND P0, #0xFF00 ; A.f2 + * 5: T3 = AND P1, #0xFF00 ; B.f2 + * 6: CMP T2, T3 ; unit 2 (last_cmp) + * 7: JUMPIF != -> L99 + * + * Both units share bases P0/P1, target L99; masks per unit are symmetric + * (mA==mB). union_mask = 0x00FF | 0xFF00 = 0xFFFF != 0xffffffff, so the AND + * masking step is needed. xor_slot = last_cmp - 2 = 4. The pass rewrites: + * @4 -> XOR Tx = P0 ^ P1 + * @5 -> AND Ty = Tx & #0xFFFF + * @6 -> CMP Ty, #0 + * and NOPs the span [2..5] except where rebuilt; the last JUMPIF survives. */ +UT_TEST(test_cmp_fuse_two_field_units_fuse) +{ + TCCIRState *ir = utb_new(); + /* IR uses TEMP 0..3; pass allocates Tx=TEMP4, Ty=TEMP5. */ + utb_alloc_temp_intervals(ir, 4, 16); + + utb_emit_and_extract(ir, 0, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 1, 1, 0x00FF, 0); + int c1 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(0, I32), utb_temp(1, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + utb_emit_and_extract(ir, 2, 0, 0xFF00, 0); + utb_emit_and_extract(ir, 3, 1, 0xFF00, 0); + int c2 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(2, I32), utb_temp(3, I32)); + int j2 = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_field_fuse(ir); + + /* One fused run -> one change. Non-vacuous: a no-op pass would leave the two + * CMPs and would fail the op assertions below. */ + UT_ASSERT_EQ(changes, 1); + + /* @4 became XOR Tx = P0 ^ P1 (xor_slot = last_cmp(6) - 2 = 4). */ + int xor_slot = 4; + UT_ASSERT_EQ(utb_op(ir, xor_slot), TCCIR_OP_XOR); + UT_ASSERT_EQ(utb_vreg(utb_dest(ir, xor_slot)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 4)); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, xor_slot)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_PARAM, 0)); + UT_ASSERT_EQ(utb_vreg(utb_src2(ir, xor_slot)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_PARAM, 1)); + + /* @5 became AND Ty = Tx & #0xFFFF (union mask of the two fields). */ + int and_slot = 5; + UT_ASSERT_EQ(utb_op(ir, and_slot), TCCIR_OP_AND); + UT_ASSERT_EQ(utb_vreg(utb_dest(ir, and_slot)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 5)); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, and_slot)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 4)); + UT_ASSERT(irop_is_immediate(utb_src2(ir, and_slot))); + UT_ASSERT_EQ((uint32_t)irop_get_imm64_ex(ir, utb_src2(ir, and_slot)), 0xFFFFu); + + /* The surviving CMP (last_cmp) is now `CMP Ty, #0`. */ + UT_ASSERT_EQ(utb_op(ir, c2), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, c2)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 5)); + UT_ASSERT(irop_is_immediate(utb_src2(ir, c2))); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, utb_src2(ir, c2)), 0); + + /* The first unit's CMP was NOP'd; the last JUMPIF survives unchanged. */ + UT_ASSERT_EQ(utb_op(ir, c1), TCCIR_OP_NOP); + UT_ASSERT_EQ(utb_op(ir, j2), TCCIR_OP_JUMPIF); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, utb_src1(ir, j2)), UT_TOK_NE); + UT_ASSERT_EQ(utb_dest(ir, j2).u.imm32, LBL); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------ NEGATIVE tests */ + +/* is_lval / memory-deref guard (Tier-1 bug class): identical to the positive + * case, except unit 2's base word A is read as an lvalue (P0 with is_lval=1). + * cmpf_same_base() compares is_lval first and refuses to line two bases up when + * the flags differ, so the forward walk breaks after unit 1, units stays 1, and + * nothing is fused. A pass that ignored the lvalue flag would (incorrectly) + * fuse a register field with a memory dereference here. */ +UT_TEST(test_cmp_fuse_lval_base_blocks_fusion) +{ + TCCIRState *ir = utb_new(); + utb_alloc_temp_intervals(ir, 4, 16); + + utb_emit_and_extract(ir, 0, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 1, 1, 0x00FF, 0); + int c1 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(0, I32), utb_temp(1, I32)); + int j1 = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + /* unit 2: base word A is an lvalue (memory) — differs from unit 1's P0. */ + utb_emit_and_extract(ir, 2, 0, 0xFF00, 1); + utb_emit_and_extract(ir, 3, 1, 0xFF00, 0); + int c2 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(2, I32), utb_temp(3, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_field_fuse(ir); + + /* Blocked: no change, both CMPs preserved. */ + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, c1), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, c2), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, j1), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* Asymmetric-mask guard: a single unit whose two compared sides extract + * *different* fields (mA = 0x00FF, mB = 0xFF00). The pass requires mA == mB for + * a clean field compare; here mA != mB, so the unit is rejected outright. */ +UT_TEST(test_cmp_fuse_asymmetric_mask_no_fuse) +{ + TCCIRState *ir = utb_new(); + utb_alloc_temp_intervals(ir, 4, 16); + + utb_emit_and_extract(ir, 0, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 1, 1, 0xFF00, 0); /* different mask than side A */ + int c1 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(0, I32), utb_temp(1, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + /* a second matching unit, so only the mask asymmetry is what blocks it */ + utb_emit_and_extract(ir, 2, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 3, 1, 0xFF00, 0); + int c2 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(2, I32), utb_temp(3, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_field_fuse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, c1), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, c2), TCCIR_OP_CMP); + + utb_free(ir); + return 0; +} + +/* Run-length guard: a single field-compare unit (no second `!=`-to-same-label + * unit) has nothing to OR together; units < 2 -> no fusion. */ +UT_TEST(test_cmp_fuse_single_unit_no_fuse) +{ + TCCIRState *ir = utb_new(); + utb_alloc_temp_intervals(ir, 4, 16); + + utb_emit_and_extract(ir, 0, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 1, 1, 0x00FF, 0); + int c1 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(0, I32), utb_temp(1, I32)); + int j1 = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_NE, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_field_fuse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, c1), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, j1), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* Condition guard: the same two-unit shape, but the branches are `==` (TOK_EQ), + * not `!=`. The OR-of-inequalities identity only holds for `!=`, so the pass + * skips the run entirely (the outer loop's TOK_NE filter). */ +UT_TEST(test_cmp_fuse_non_ne_condition_no_fuse) +{ + TCCIRState *ir = utb_new(); + utb_alloc_temp_intervals(ir, 4, 16); + + utb_emit_and_extract(ir, 0, 0, 0x00FF, 0); + utb_emit_and_extract(ir, 1, 1, 0x00FF, 0); + int c1 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(0, I32), utb_temp(1, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_EQ, I32), UTB_NONE); + utb_emit_and_extract(ir, 2, 0, 0xFF00, 0); + utb_emit_and_extract(ir, 3, 1, 0xFF00, 0); + int c2 = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(2, I32), utb_temp(3, I32)); + utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(LBL, I32), utb_imm(UT_TOK_EQ, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_field_fuse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, c1), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, c2), TCCIR_OP_CMP); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_cmp_fuse) +{ + UT_COVERS("cmp_field_fuse"); + UT_RUN(test_cmp_fuse_two_field_units_fuse); + UT_RUN(test_cmp_fuse_lval_base_blocks_fusion); + UT_RUN(test_cmp_fuse_asymmetric_mask_no_fuse); + UT_RUN(test_cmp_fuse_single_unit_no_fuse); + UT_RUN(test_cmp_fuse_non_ne_condition_no_fuse); +} diff --git a/tests/unit/arm/armv8m/test_opt_cmpfold.c b/tests/unit/arm/armv8m/test_opt_cmpfold.c new file mode 100644 index 00000000..fb070417 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_cmpfold.c @@ -0,0 +1,172 @@ +/* + * test_opt_cmpfold.c - suite for the comparison fold/fuse passes + * (ir/opt_constprop.c: tcc_ir_opt_cmp_expr_fold / tcc_ir_opt_cmp_const_offset_fold, + * ir/opt_cmp_fuse.c: tcc_ir_opt_cmp_field_fuse). + * + * These isolated tests drive tcc_ir_opt_cmp_const_offset_fold, the entry point + * that is cleanest to exercise on a hand-built IR: it needs no live-interval + * arrays nor a real Sym, only the linear def-finding helpers. + * + * cmp_const_offset_fold collapses `A = B (+/-) K ; CMP A,B ; JUMPIF cond` + * into a constant branch by substituting A = B + K (so the comparison reduces + * to `K cond 0`). When the condition is statically true it rewrites the CMP + * to NOP and the JUMPIF to an unconditional JUMP (then runs DCE); when false + * it NOPs both. Guards (asserted as no-ops here): the ADD base's lval-ness + * must match the CMP operand's (the historical wide-string-literal heap crash + * came from a missing is_lval guard in these cmp-fold passes), the condition + * must be signed or EQ/NE, and K must be non-zero. + * + * A hand-built IR sequence is run through the bare pass entry point and the + * resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry points (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_cmp_expr_fold(TCCIRState *ir); +int tcc_ir_opt_cmp_const_offset_fold(TCCIRState *ir); +int tcc_ir_opt_cmp_field_fuse(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 +#define I64 IROP_BTYPE_INT64 + +/* Comparison condition tokens (see evaluate_compare_condition in opt_utils.c). */ +#define TOK_GT 0x9f /* signed > */ +#define TOK_LT 0x9c /* signed < */ +#define TOK_ULT 0x92 /* unsigned < */ + +/* ------------------------------------------------------------------ tests */ + +/* POSITIVE: `A = B + 5 ; CMP A,B ; JUMPIF >` reduces to `5 > 0` == true. + * i0: ADD T1 <- T0 + 5 + * i1: CMP T1, T0 + * i2: JUMPIF (>) -> #4 + * i3: RETURNVOID (dead after fold: only reachable via fall-through + * from the JUMPIF, which became an unconditional JUMP) + * i4: RETURNVOID (jump target) + * After fold: CMP -> NOP, JUMPIF -> unconditional JUMP to the same target. */ +UT_TEST(test_cmpfold_offset_signed_true_folds_to_jump) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(5, I32)); + int icmp = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(1, I32), utb_temp(0, I32)); + int ijmp = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(4, I32), utb_imm(TOK_GT, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); + + int changes = tcc_ir_opt_cmp_const_offset_fold(ir); + + /* The pass fired: CMP folded away, JUMPIF became an unconditional JUMP to the + * original target. changes also includes the follow-up DCE, so assert > 0. */ + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, icmp), TCCIR_OP_NOP); + UT_ASSERT_EQ(utb_op(ir, ijmp), TCCIR_OP_JUMP); + UT_ASSERT_EQ(utb_dest(ir, ijmp).u.imm32, 4); + + utb_free(ir); + return 0; +} + +/* GUARD (the historical is_lval bug): the ADD base is a plain value `T0` but the + * CMP's second operand is a deref `*(T0)` (is_lval). `*(p)+K` (a loaded value) + * does not make `A == p + K` provable from `B == p`, so the pass must NOT fold. + * i0: ADD T1 <- T0 + 5 (base T0 NOT lval) + * i1: CMP T1, *(T0) (src2 = T0 with is_lval = 1) + * i2: JUMPIF (>) -> #4 */ +UT_TEST(test_cmpfold_offset_lval_base_mismatch_no_fold) +{ + TCCIRState *ir = utb_new(); + + IROperand t0_deref = utb_temp(0, I32); + t0_deref.is_lval = 1; + + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(5, I32)); + int icmp = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(1, I32), t0_deref); + int ijmp = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(4, I32), utb_imm(TOK_GT, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_const_offset_fold(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, icmp), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, ijmp), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: unsigned conditions need an overflow proof and are skipped. Same + * foldable arithmetic shape as the positive test but with an unsigned `<`. */ +UT_TEST(test_cmpfold_offset_unsigned_cond_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(5, I32)); + int icmp = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(1, I32), utb_temp(0, I32)); + int ijmp = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(4, I32), utb_imm(TOK_ULT, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_const_offset_fold(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, icmp), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, ijmp), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: a zero offset (`A = B + 0`) gives delta 0; the pass bails on k == 0 + * (the comparison is genuinely `B vs B`, handled elsewhere), so no fold here. */ +UT_TEST(test_cmpfold_offset_zero_delta_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(0, I32)); + int icmp = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(1, I32), utb_temp(0, I32)); + int ijmp = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(4, I32), utb_imm(TOK_LT, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_const_offset_fold(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, icmp), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, ijmp), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: no ADD/SUB feeding either CMP operand, so there is no provable + * constant offset and nothing folds. */ +UT_TEST(test_cmpfold_offset_no_arith_def_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_imm(7, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(3, I32), UTB_NONE); + int icmp = utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_temp(1, I32), utb_temp(0, I32)); + int ijmp = utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(5, I32), utb_imm(TOK_LT, I32), UTB_NONE); + + int changes = tcc_ir_opt_cmp_const_offset_fold(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, icmp), TCCIR_OP_CMP); + UT_ASSERT_EQ(utb_op(ir, ijmp), TCCIR_OP_JUMPIF); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_cmpfold) +{ + UT_COVERS("cmp_fold"); + UT_RUN(test_cmpfold_offset_signed_true_folds_to_jump); + UT_RUN(test_cmpfold_offset_lval_base_mismatch_no_fold); + UT_RUN(test_cmpfold_offset_unsigned_cond_no_fold); + UT_RUN(test_cmpfold_offset_zero_delta_no_fold); + UT_RUN(test_cmpfold_offset_no_arith_def_no_fold); +} diff --git a/tests/unit/arm/armv8m/test_opt_constfold.c b/tests/unit/arm/armv8m/test_opt_constfold.c new file mode 100644 index 00000000..0bc02dc9 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_constfold.c @@ -0,0 +1,254 @@ +/* + * test_opt_constfold.c - suite for ir/opt_constfold.c + * + * Covers two name-gated call-folding passes from ir/opt_constfold.c: + * + * - tcc_ir_opt_self_copy_elim : NOPs a memcpy/memmove (or AAPCS aligned + * variant) call whose dst and src arguments are the same pure expression + * (a self-copy). FUNCCALLVAL is rewritten to `ASSIGN dst`, FUNCCALLVOID + * to NOP, and the param marshalling is NOP'd. + * - tcc_ir_opt_float_narrowing : collects __aeabi_f2d / __aeabi_d2f + * conversion calls and narrows floor()/ceil()/fabs()/... double helpers to + * their float variant when an argument is an f2d result. + * + * HARNESS LIMITATION (important — see FINDINGS in the agent report): + * Both passes decide whether to fire SOLELY from the callee name returned by + * get_tok_str(callee->v). In this isolated host harness get_tok_str() is the + * shared base stub (tests/unit/arm/armv8m/stubs.c -> built as extra_stubs.o) + * which returns the constant "?" for EVERY token and is a strong, unoverridable + * global. Consequently neither pass can ever match a real helper name here, so + * a "true positive" (the pass actually folding) is structurally unreachable in + * this harness. These two passes are therefore exercised as GUARD passes: a + * fully-formed self-copy / f2d->func->d2f sequence is built (so the entire + * collection + param-equality + call-id machinery runs), and we assert the pass + * correctly declines to fire because the name does not match. Each test would + * FAIL (changed != 0, op rewritten) if the name gate were ever dropped or the + * pass over-fired, so the assertions are non-vacuous. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry points (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_self_copy_elim(TCCIRState *ir); +int tcc_ir_opt_float_narrowing(TCCIRState *ir); + +/* Frontend link stubs (sym_push2 / external_global_sym / tok_alloc_const / + * global_stack / elfsym) now live in stubs.c so the combined unit-test link + * has a single definition. They are unreachable at runtime here because the + * name gate in float_narrowing never matches under the "?" get_tok_str stub. */ + +#define I32 IROP_BTYPE_INT32 +#define F32 IROP_BTYPE_FLOAT32 +#define F64 IROP_BTYPE_FLOAT64 + +/* ----------------------------------------------------------- helpers */ + +/* Build a SYMREF operand carrying a freshly-pooled callee Sym. The Sym's `v` + * token is irrelevant in this harness (get_tok_str ignores it and returns "?"), + * but irop_get_sym_ex() must resolve to a non-NULL Sym for the pass to even + * reach the name check, so a real pool entry is required. */ +static IROperand utb_callee(TCCIRState *ir, Sym *sym) +{ + sym->v = 0; + uint32_t sidx = tcc_ir_pool_add_symref(ir, sym, 0, 0); + return irop_make_symref(0, sidx, 0, 0, 0, I32); +} + +/* ----------------------------------------------------- self_copy_elim tests */ + +/* GUARD (would-fold-if-name-matched): a FUNCCALLVAL whose callee resolves to a + * valid Sym and whose param0 (dst) and param1 (src) are the *identical* pure + * value T0 — i.e. exactly the self-copy shape the pass targets. The only thing + * stopping the fold is that get_tok_str returns "?", which is not memcpy-like. + * The pass must leave the call (and its params) untouched and return 0. + * + * This exercises the full path: the FUNCCALLVAL is detected, the callee Sym is + * resolved, the name is looked up, and the memcpy-name gate rejects it BEFORE + * the (would-succeed) param-equality test. If the name gate were removed the + * call would be rewritten to ASSIGN and this test would FAIL. + * + * FUNCPARAMVAL T0, param0 (dst) + * FUNCPARAMVAL T0, param1 (src == dst, same pure expr) + * FUNCPARAMVAL #16, param2 (n) + * T1 = FUNCCALLVAL , call_id=1 argc=3 */ +UT_TEST(test_self_copy_elim_non_memcpy_name_no_fold) +{ + TCCIRState *ir = utb_new(); + tcc_ir_pools_init(ir); /* needs the symref pool for the callee operand */ + + static Sym callee_sym; + IROperand callee = utb_callee(ir, &callee_sym); + + const int call_id = 1; + int i_p0 = utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, I32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(call_id, 0), I32)); + int i_p1 = utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, I32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(call_id, 1), I32)); + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_imm(16, I32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(call_id, 2), I32)); + int i_call = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(1, I32), callee, + utb_imm((int32_t)TCCIR_ENCODE_CALL(call_id, 3), I32)); + + int changes = tcc_ir_opt_self_copy_elim(ir); + + /* Name does not match memcpy-like -> nothing rewritten or NOP'd. */ + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i_call), TCCIR_OP_FUNCCALLVAL); + UT_ASSERT_EQ(utb_op(ir, i_p0), TCCIR_OP_FUNCPARAMVAL); + UT_ASSERT_EQ(utb_op(ir, i_p1), TCCIR_OP_FUNCPARAMVAL); + + utb_free(ir); + return 0; +} + +/* GUARD: a non-call instruction stream contains no FUNCCALLVAL/FUNCCALLVOID, so + * the pass's outer loop never enters the body. Pure structural negative: even a + * trivial ASSIGN/RETURNVALUE pair must be returned untouched with 0 changes. + * This pins the "no calls -> no work" behaviour independent of get_tok_str. */ +UT_TEST(test_self_copy_elim_no_calls_no_fold) +{ + TCCIRState *ir = utb_new(); + + int i_assign = utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(7, I32), UTB_NONE); + int i_ret = utb_emit(ir, TCCIR_OP_RETURNVALUE, UTB_NONE, utb_temp(0, I32), UTB_NONE); + + int changes = tcc_ir_opt_self_copy_elim(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i_assign), TCCIR_OP_ASSIGN); + UT_ASSERT_EQ(utb_op(ir, i_ret), TCCIR_OP_RETURNVALUE); + + utb_free(ir); + return 0; +} + +/* GUARD: a FUNCCALLVAL whose src1 is NOT a SYMREF (here an immediate) — so + * irop_get_sym_ex() returns NULL and the pass `continue`s at the !callee check, + * before any name lookup. Confirms the null-callee early-out leaves the call + * intact and reports 0 changes. Also a NULL-deref smoke check for the helper. */ +UT_TEST(test_self_copy_elim_null_callee_no_fold) +{ + TCCIRState *ir = utb_new(); + + const int call_id = 2; + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, I32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(call_id, 0), I32)); + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, I32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(call_id, 1), I32)); + /* src1 is an immediate, not a SYMREF -> no callee Sym. */ + int i_call = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(1, I32), utb_imm(0, I32), + utb_imm((int32_t)TCCIR_ENCODE_CALL(call_id, 2), I32)); + + int changes = tcc_ir_opt_self_copy_elim(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i_call), TCCIR_OP_FUNCCALLVAL); + + utb_free(ir); + return 0; +} + +/* NULL-IR guard: tcc_ir_opt_self_copy_elim(NULL) must early-return 0 and not + * dereference the state pointer. */ +UT_TEST(test_self_copy_elim_null_ir) +{ + UT_ASSERT_EQ(tcc_ir_opt_self_copy_elim(NULL), 0); + return 0; +} + +/* ---------------------------------------------------- float_narrowing tests */ + +/* GUARD (would-narrow-if-names-matched): a textbook f2d -> floor -> d2f chain + * (the exact Case-1 shape tcc_ir_opt_float_narrowing rewrites). Phase 1 scans + * for __aeabi_f2d / __aeabi_d2f by name; under the "?" stub it finds none, so + * num_f2d == 0 and the pass returns 0 at the early-out, leaving every call and + * param intact. If the f2d/d2f name gate were dropped, the floor call would be + * narrowed and the f2d/d2f calls NOP'd, failing these assertions. + * + * FUNCPARAMVAL Tf(float), param0 (call_id 1) + * Td = FUNCCALLVAL (would be __aeabi_f2d: float->double) + * FUNCPARAMVAL Td(double), param0 (call_id 2) + * Tr = FUNCCALLVAL (would be floor: double->double) + * FUNCPARAMVAL Tr(double), param0 (call_id 3) + * Tf2 = FUNCCALLVAL (would be __aeabi_d2f: double->float) */ +UT_TEST(test_float_narrowing_unmatched_names_no_fold) +{ + TCCIRState *ir = utb_new(); + tcc_ir_pools_init(ir); + + static Sym f2d_sym, floor_sym, d2f_sym; + IROperand f2d_callee = utb_callee(ir, &f2d_sym); + IROperand floor_callee = utb_callee(ir, &floor_sym); + IROperand d2f_callee = utb_callee(ir, &d2f_sym); + + /* f2d: float Tf(0) -> double Td(1) */ + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, F32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(1, 0), I32)); + int i_f2d = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(1, F64), f2d_callee, + utb_imm((int32_t)TCCIR_ENCODE_CALL(1, 1), I32)); + /* floor: double Td(1) -> double Tr(2) */ + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(1, F64), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(2, 0), I32)); + int i_floor = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(2, F64), floor_callee, + utb_imm((int32_t)TCCIR_ENCODE_CALL(2, 1), I32)); + /* d2f: double Tr(2) -> float Tf2(3) */ + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(2, F64), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(3, 0), I32)); + int i_d2f = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(3, F32), d2f_callee, + utb_imm((int32_t)TCCIR_ENCODE_CALL(3, 1), I32)); + + int changes = tcc_ir_opt_float_narrowing(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i_f2d), TCCIR_OP_FUNCCALLVAL); + UT_ASSERT_EQ(utb_op(ir, i_floor), TCCIR_OP_FUNCCALLVAL); + UT_ASSERT_EQ(utb_op(ir, i_d2f), TCCIR_OP_FUNCCALLVAL); + + utb_free(ir); + return 0; +} + +/* GUARD: too few instructions. tcc_ir_opt_float_narrowing requires at least 4 + * instructions (n < 4 -> return 0) before doing any scanning. A 2-instruction + * f2d-shaped pair must short-circuit to 0 with the IR untouched. */ +UT_TEST(test_float_narrowing_too_few_instructions_no_fold) +{ + TCCIRState *ir = utb_new(); + tcc_ir_pools_init(ir); + + static Sym f2d_sym; + IROperand f2d_callee = utb_callee(ir, &f2d_sym); + + utb_emit(ir, TCCIR_OP_FUNCPARAMVAL, UTB_NONE, utb_temp(0, F32), + utb_imm((int32_t)TCCIR_ENCODE_PARAM(1, 0), I32)); + int i_call = utb_emit(ir, TCCIR_OP_FUNCCALLVAL, utb_temp(1, F64), f2d_callee, + utb_imm((int32_t)TCCIR_ENCODE_CALL(1, 1), I32)); + + int changes = tcc_ir_opt_float_narrowing(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i_call), TCCIR_OP_FUNCCALLVAL); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_constfold) +{ + UT_COVERS("self_copy_elim"); + UT_COVERS("float_narrowing"); + UT_RUN(test_self_copy_elim_non_memcpy_name_no_fold); + UT_RUN(test_self_copy_elim_no_calls_no_fold); + UT_RUN(test_self_copy_elim_null_callee_no_fold); + UT_RUN(test_self_copy_elim_null_ir); + UT_RUN(test_float_narrowing_unmatched_names_no_fold); + UT_RUN(test_float_narrowing_too_few_instructions_no_fold); +} diff --git a/tests/unit/arm/armv8m/test_opt_constprop.c b/tests/unit/arm/armv8m/test_opt_constprop.c new file mode 100644 index 00000000..9aa08321 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_constprop.c @@ -0,0 +1,364 @@ +/* + * test_opt_constprop.c - suite for ir/opt_constprop.c (constant propagation) + * + * Covers TWO entry points from the same TU: + * + * 1. tcc_ir_opt_const_var_prop — finds VAR vregs assigned exactly once with an + * immediate (`ASSIGN Vp <- #k`, def_count==1, not addrtaken) and rewrites + * later src1/src2 uses of that VAR with the immediate. When the only uses + * are rewritten, the defining ASSIGN is NOP-ed (Phase 3 dead-store cleanup); + * a LOAD whose address operand folds to a constant becomes an ASSIGN. + * + * 2. tcc_ir_opt_const_prop — folds constants into arithmetic and compares: + * `T0 = #5 ADD #3` collapses to `T0 = ASSIGN #8`, a single-def immediate VAR + * propagates into a use, and one-constant algebraic identities (X+0 -> X, + * X*0 -> 0) simplify. Non-constant operands are left alone. + * + * Key behaviours / guards verified here: + * - const_var_prop POSITIVE: a single-def immediate VAR folds into a later + * arithmetic use (src operand becomes the immediate) and, with no other + * uses, the def is NOP-ed -> changes > 0. + * - const_var_prop POSITIVE: LOAD of a constant VAR address flips to ASSIGN. + * - const_var_prop GUARD: a VAR whose interval->addrtaken is set AND whose + * address is taken by a *live* LEA must NOT propagate. changes == 0. + * - const_var_prop NEGATIVE: multiply-defined / non-immediate-source VARs are + * not constant and are not propagated. changes == 0. + * - const_prop POSITIVE: two-constant fold of an ADD into a single ASSIGN + * (no VAR dests -> needs no live intervals). + * - const_prop POSITIVE: single-def immediate VAR propagated into an ADD and + * then constant-folded to ASSIGN. + * - const_prop POSITIVE: X + 0 -> X algebraic simplify (ADD becomes ASSIGN). + * - const_prop NEGATIVE: an ADD of two non-constant TEMPs is not folded. + * + * Both passes call tcc_ir_get_live_interval() for every VAR destination, which + * exit(1)s when ir->variables_live_intervals is NULL/zero-sized (utb_new() + * leaves it so). Tests that emit VAR destinations therefore allocate a zeroed + * interval table first; that table is also where the addrtaken guard reads. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry points (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_const_var_prop(TCCIRState *ir); +int tcc_ir_opt_const_prop(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 +#define I64 IROP_BTYPE_INT64 + +/* Encoded vreg helpers for assertions. */ +#define VR_TMP(p) TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, (p)) +#define VR_VAR(p) TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_VAR, (p)) + +/* Both passes dereference ir->variables_live_intervals[pos] for every VAR + * destination they see. utb_new() zeroes that pointer/size, which would make + * tcc_ir_get_live_interval() report "out of bounds" and exit(1). Allocate a + * zeroed interval table large enough for all VAR positions a test uses. */ +static void utb_alloc_var_intervals(TCCIRState *ir, int count) +{ + ir->variables_live_intervals = + (IRLiveInterval *)tcc_mallocz(sizeof(IRLiveInterval) * count); + ir->variables_live_intervals_size = count; +} + +/* ============================================================= const_var_prop */ + +/* POSITIVE: a single-def immediate VAR folds into a later ADD use. + * V0 <- #5 [constant def] + * T0 = V0 ADD #3 -> src1 rewritten to #5 + * V0 then has no remaining uses, so the def ASSIGN is NOP-ed (Phase 3). + * changes > 0; the ADD's src1 becomes the immediate 5. */ +UT_TEST(test_constvarprop_imm_var_folds_into_use) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + + int idef = utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(5, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_var(0, I32), utb_imm(3, I32)); + + int changes = tcc_ir_opt_const_var_prop(ir); + + UT_ASSERT(changes > 0); + + /* The ADD's src1 is now the immediate 5 (no longer a VAR reference). */ + IROperand s1 = utb_src1(ir, iadd); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 5); + + /* With the only use rewritten, the defining ASSIGN is dead and NOP-ed. */ + UT_ASSERT_EQ(utb_op(ir, idef), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* POSITIVE (LOAD -> ASSIGN rewrite): a LOAD whose address operand is a constant + * VAR folds: src1 becomes the immediate AND the op flips LOAD -> ASSIGN, because + * the local's address now resolves to a known constant value. + * V0 <- #7 + * T0 = LOAD V0 -> T0 = ASSIGN #7 */ +UT_TEST(test_constvarprop_load_of_const_var_becomes_assign) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(7, I32), UTB_NONE); + int iload = utb_emit(ir, TCCIR_OP_LOAD, utb_temp(0, I32), utb_var(0, I32), UTB_NONE); + + int changes = tcc_ir_opt_const_var_prop(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, iload), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, iload); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 7); + + utb_free(ir); + return 0; +} + +/* GUARD (address-taken): V0 is single-def immediate, BUT its address is taken by + * a live LEA and interval->addrtaken is set, so the value can be mutated through + * the alias. The pass must NOT propagate V0 into the later use. + * + * V0 <- #5 + * V1 = &V0 [LEA: address of V0 taken] + * T0 = V1 ADD #1 [reads V1 -> the LEA is "live", so refresh keeps addrtaken] + * T1 = V0 ADD #9 [use of V0 that must remain a VAR reference] + * + * Without a live LEA, refresh_stale_var_addrtaken() would clear addrtaken and + * the value would propagate; the live LEA + addrtaken flag is what blocks it. */ +UT_TEST(test_constvarprop_addrtaken_var_not_propagated) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + /* Mark V0's address as taken (frontend would set this for `&v`). */ + ir->variables_live_intervals[0].addrtaken = 1; + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_LEA, utb_var(1, I32), utb_var(0, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_var(1, I32), utb_imm(1, I32)); + int iuse = utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_var(0, I32), utb_imm(9, I32)); + + int changes = tcc_ir_opt_const_var_prop(ir); + + UT_ASSERT_EQ(changes, 0); + /* The use of V0 is untouched: src1 still references VAR 0, not an immediate. */ + IROperand s1 = utb_src1(ir, iuse); + UT_ASSERT_EQ(irop_is_immediate(s1), 0); + UT_ASSERT_EQ(utb_vreg(s1), VR_VAR(0)); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (multiply defined): a VAR assigned an immediate twice is not a single + * constant (def_count > 1 -> is_constant cleared), so it is not propagated. + * V0 <- #5 + * V0 <- #6 + * T0 = V0 ADD #1 -> NOT rewritten (still V0) */ +UT_TEST(test_constvarprop_multiply_defined_not_propagated) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(6, I32), UTB_NONE); + int iuse = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_var(0, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_const_var_prop(ir); + + UT_ASSERT_EQ(changes, 0); + IROperand s1 = utb_src1(ir, iuse); + UT_ASSERT_EQ(irop_is_immediate(s1), 0); + UT_ASSERT_EQ(utb_vreg(s1), VR_VAR(0)); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (non-immediate source): a VAR assigned from another vreg (not an + * immediate, not a symref) is not constant, so it is not propagated. + * V0 <- T9 (source is a TEMP, not a constant) + * T0 = V0 ADD #1 -> NOT rewritten (still V0) */ +UT_TEST(test_constvarprop_nonconst_source_not_propagated) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_temp(9, I32), UTB_NONE); + int iuse = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_var(0, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_const_var_prop(ir); + + UT_ASSERT_EQ(changes, 0); + IROperand s1 = utb_src1(ir, iuse); + UT_ASSERT_EQ(irop_is_immediate(s1), 0); + UT_ASSERT_EQ(utb_vreg(s1), VR_VAR(0)); + + utb_free(ir); + return 0; +} + +/* ================================================================= const_prop */ + +/* POSITIVE (two-constant fold): const_prop folds an arithmetic op whose both + * operands are immediates into a single ASSIGN of the computed value. + * T0 = #5 ADD #3 -> T0 = ASSIGN #8 (src2 cleared) + * No VAR destinations exist, so no live-interval table is needed. */ +UT_TEST(test_constprop_two_const_add_folds) +{ + TCCIRState *ir = utb_new(); + + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(5, I32), utb_imm(3, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT(changes > 0); + /* The ADD collapses to an ASSIGN of the constant result. */ + UT_ASSERT_EQ(utb_op(ir, iadd), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, iadd); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 8); + + utb_free(ir); + return 0; +} + +/* POSITIVE (two-constant fold, MUL): demonstrates folding is not ADD-specific. + * T0 = #6 MUL #7 -> T0 = ASSIGN #42 */ +UT_TEST(test_constprop_two_const_mul_folds) +{ + TCCIRState *ir = utb_new(); + + int imul = utb_emit(ir, TCCIR_OP_MUL, utb_temp(0, I32), utb_imm(6, I32), utb_imm(7, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, imul), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, imul); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 42); + + utb_free(ir); + return 0; +} + +/* POSITIVE (VAR const propagated then folded): const_prop first propagates a + * single-def immediate VAR into the ADD's src1, then folds the now all-constant + * ADD into an ASSIGN. + * V0 <- #5 + * T0 = V0 ADD #3 -> T0 = ASSIGN #8 */ +UT_TEST(test_constprop_var_const_propagated_and_folded) +{ + TCCIRState *ir = utb_new(); + utb_alloc_var_intervals(ir, 4); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(5, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_var(0, I32), utb_imm(3, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, iadd), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, iadd); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 8); + + utb_free(ir); + return 0; +} + +/* POSITIVE (algebraic simplify): X + 0 = X. With a non-constant src1 and a + * constant 0 in src2, const_prop converts the ADD into an ASSIGN that copies + * src1 unchanged (the non-constant operand is preserved, src2 cleared). + * T0 = T1 ADD #0 -> T0 = ASSIGN T1 */ +UT_TEST(test_constprop_add_zero_simplifies_to_copy) +{ + TCCIRState *ir = utb_new(); + + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_temp(1, I32), utb_imm(0, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT(changes > 0); + /* Becomes a plain copy of the non-constant src1. */ + UT_ASSERT_EQ(utb_op(ir, iadd), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, iadd); + UT_ASSERT_EQ(irop_is_immediate(s1), 0); + UT_ASSERT_EQ(utb_vreg(s1), VR_TMP(1)); + + utb_free(ir); + return 0; +} + +/* POSITIVE (algebraic simplify): X * 0 = 0. const_prop replaces the whole op + * with an ASSIGN of constant 0, even though src1 is non-constant. + * T0 = T1 MUL #0 -> T0 = ASSIGN #0 */ +UT_TEST(test_constprop_mul_zero_simplifies_to_zero) +{ + TCCIRState *ir = utb_new(); + + int imul = utb_emit(ir, TCCIR_OP_MUL, utb_temp(0, I32), utb_temp(1, I32), utb_imm(0, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, imul), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, imul); + UT_ASSERT_EQ(irop_is_immediate(s1), 1); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, s1), 0); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: an ADD of two non-constant TEMPs has nothing to fold or simplify + * (neither operand is an immediate, no identity applies) -> no change, the op + * stays an ADD with both register operands intact. + * T0 = T1 ADD T2 -> unchanged */ +UT_TEST(test_constprop_two_nonconst_not_folded) +{ + TCCIRState *ir = utb_new(); + + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_temp(1, I32), utb_temp(2, I32)); + + int changes = tcc_ir_opt_const_prop(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, iadd), TCCIR_OP_ADD); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(1)); + UT_ASSERT_EQ(utb_vreg(utb_src2(ir, iadd)), VR_TMP(2)); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_constprop) +{ + UT_COVERS("const_var_prop"); + UT_COVERS("const_prop"); + + /* const_var_prop */ + UT_RUN(test_constvarprop_imm_var_folds_into_use); + UT_RUN(test_constvarprop_load_of_const_var_becomes_assign); + UT_RUN(test_constvarprop_addrtaken_var_not_propagated); + UT_RUN(test_constvarprop_multiply_defined_not_propagated); + UT_RUN(test_constvarprop_nonconst_source_not_propagated); + + /* const_prop */ + UT_RUN(test_constprop_two_const_add_folds); + UT_RUN(test_constprop_two_const_mul_folds); + UT_RUN(test_constprop_var_const_propagated_and_folded); + UT_RUN(test_constprop_add_zero_simplifies_to_copy); + UT_RUN(test_constprop_mul_zero_simplifies_to_zero); + UT_RUN(test_constprop_two_nonconst_not_folded); +} diff --git a/tests/unit/arm/armv8m/test_opt_copyprop.c b/tests/unit/arm/armv8m/test_opt_copyprop.c new file mode 100644 index 00000000..5f9bc079 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_copyprop.c @@ -0,0 +1,266 @@ +/* + * test_opt_copyprop.c - suite for ir/opt_copyprop.c (copy propagation) + * + * tcc_ir_opt_copy_prop tracks ASSIGN "copies" of the form + * TMP:X <- VAR:Y | PARAM:Y | TMP:Y (src not constant, not lval) + * and rewrites later uses of TMP:X with the recorded source operand, as long + * as the source has not been redefined between the copy and the use and no + * basic-block boundary / terminator / FUNCCALL has cleared the copy table. + * + * Key guards verified here: + * - lval (DEREF) uses keep their is_lval / load-width bits when the source is + * substituted in, and a VAR/PARAM source is NOT propagated into an lval use + * (only a TMP source is). + * - ASSIGN with an lval source is a LOAD, not a copy, so it is NOT recorded. + * - a constant source is not a copy and is NOT recorded. + * - redefining the source before the use invalidates the copy. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_copy_prop(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 +#define I16 IROP_BTYPE_INT16 +#define I64 IROP_BTYPE_INT64 + +/* Encoded vreg helpers for assertions. */ +#define VR_TMP(p) TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, (p)) +#define VR_VAR(p) TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_VAR, (p)) +#define VR_PARAM(p) TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_PARAM, (p)) + +/* ------------------------------------------------------------------ tests */ + +/* POSITIVE: a plain VAR copy propagates into an arithmetic use. + * T1 <- V0 [ASSIGN copy] + * T2 = T1 ADD #1 -> src1 rewritten to V0 + * changes > 0, and T2.src1 becomes V0. */ +UT_TEST(test_copyprop_var_copy_propagates_to_add) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_var(0, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(1, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT(changes > 0); + /* The ADD's src1 must now reference the copy source V0, not T1. */ + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_VAR(0)); + UT_ASSERT_EQ(utb_op(ir, iadd), TCCIR_OP_ADD); + + utb_free(ir); + return 0; +} + +/* POSITIVE: a TMP->TMP copy propagates into BOTH src1 and src2 of one use. + * T1 <- T0 + * T3 = T1 ADD T1 -> both operands rewritten to T0 (two changes) */ +UT_TEST(test_copyprop_tmp_copy_propagates_both_operands) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_temp(0, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(3, I32), utb_temp(1, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + /* src1 and src2 are each rewritten -> at least two propagations. */ + UT_ASSERT(changes >= 2); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(0)); + UT_ASSERT_EQ(utb_vreg(utb_src2(ir, iadd)), VR_TMP(0)); + + utb_free(ir); + return 0; +} + +/* is_lval PRESERVATION: a TMP->TMP copy of an address propagates into an lval + * (DEREF) use while keeping the deref + load-width bits taken from the use site. + * T1 <- T0 (register-to-register address copy) + * T2 = LOAD T1***DEREF*** (INT16) -> src1 becomes T0 but stays lval, INT16 */ +UT_TEST(test_copyprop_lval_use_preserves_deref_and_width) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_temp(0, I32), UTB_NONE); + + /* Build the LOAD's lval src1 by hand (DEREF, narrow INT16 load). */ + IROperand load_src = utb_temp(1, I16); + load_src.is_lval = 1; + int iload = utb_emit(ir, TCCIR_OP_LOAD, utb_temp(2, I32), load_src, UTB_NONE); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT(changes > 0); + IROperand s1 = utb_src1(ir, iload); + /* Substituted to the copy source T0... */ + UT_ASSERT_EQ(utb_vreg(s1), VR_TMP(0)); + /* ...but the DEREF semantics and the use-site load width are preserved. */ + UT_ASSERT_EQ((int)s1.is_lval, 1); + UT_ASSERT_EQ(irop_get_btype(s1), I16); + + utb_free(ir); + return 0; +} + +/* GUARD (lval source NOT propagated for VAR): an lval use whose copy source is a + * VAR must NOT be rewritten, because propagating a VAR into a DEREF would extend + * its live range and can corrupt register allocation. Only TMP sources qualify. + * T1 <- V0 + * T2 = LOAD T1***DEREF*** -> NOT rewritten (still T1, still lval) */ +UT_TEST(test_copyprop_lval_use_var_source_not_propagated) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_var(0, I32), UTB_NONE); + + IROperand load_src = utb_temp(1, I32); + load_src.is_lval = 1; + int iload = utb_emit(ir, TCCIR_OP_LOAD, utb_temp(2, I32), load_src, UTB_NONE); + + int changes = tcc_ir_opt_copy_prop(ir); + + /* The lval use is left untouched; the only possible change would have been + * this propagation, so the pass must report no changes. */ + UT_ASSERT_EQ(changes, 0); + IROperand s1 = utb_src1(ir, iload); + UT_ASSERT_EQ(utb_vreg(s1), VR_TMP(1)); + UT_ASSERT_EQ((int)s1.is_lval, 1); + + utb_free(ir); + return 0; +} + +/* GUARD (ASSIGN with lval source is a LOAD, not a copy): must NOT be recorded, + * so a later use of the destination is NOT rewritten. + * T1 <- V0***DEREF*** (this is a LOAD-shaped ASSIGN) + * T2 = T1 ADD #1 -> NOT rewritten */ +UT_TEST(test_copyprop_lval_source_assign_not_recorded) +{ + TCCIRState *ir = utb_new(); + + IROperand lval_src = utb_var(0, I32); + lval_src.is_lval = 1; + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), lval_src, UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(1, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(1)); + + utb_free(ir); + return 0; +} + +/* GUARD (constant source): T1 <- #5 is not a copy; no propagation. + * T1 <- #5 + * T2 = T1 ADD #1 -> NOT rewritten */ +UT_TEST(test_copyprop_const_source_not_recorded) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_imm(5, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(1, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(1)); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (source redefined before use): the copy is invalidated when its + * source VAR is reassigned between the copy and the use, so it must NOT + * propagate past the redefinition. + * T1 <- V0 + * V0 <- #9 (redefines the source) + * T2 = T1 ADD #1 -> NOT rewritten (still T1) */ +UT_TEST(test_copyprop_source_redef_blocks_propagation) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_var(0, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_ASSIGN, utb_var(0, I32), utb_imm(9, I32), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(1, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(1)); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (btype mismatch on the copy): T9 is a 64-bit value and T10 <- T9 + * truncates to 32-bit; that ASSIGN is NOT a copy (different register width + * class), so a later use of T10 must NOT be rewritten. + * T10(INT32) <- T9(INT64) + * T11 = T10 ADD #1 -> NOT rewritten */ +UT_TEST(test_copyprop_btype_mismatch_not_recorded) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(10, I32), utb_temp(9, I64), UTB_NONE); + int iadd = utb_emit(ir, TCCIR_OP_ADD, utb_temp(11, I32), utb_temp(10, I32), utb_imm(1, I32)); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, iadd)), VR_TMP(10)); + + utb_free(ir); + return 0; +} + +/* POSITIVE (STORE dest propagation): copy of an address propagates into the + * STORE destination pointer while preserving the DEREF + store width. + * T1 <- T0 + * STORE T1***DEREF*** <- V5 -> dest pointer rewritten to T0 (still lval) */ +UT_TEST(test_copyprop_store_dest_tmp_source_propagates) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(1, I32), utb_temp(0, I32), UTB_NONE); + + /* STORE: dest = address (lval pointer), src1 = value. */ + IROperand store_addr = utb_temp(1, I32); + store_addr.is_lval = 1; + int istore = utb_emit(ir, TCCIR_OP_STORE, store_addr, utb_var(5, I32), UTB_NONE); + + int changes = tcc_ir_opt_copy_prop(ir); + + UT_ASSERT(changes > 0); + IROperand d = utb_dest(ir, istore); + UT_ASSERT_EQ(utb_vreg(d), VR_TMP(0)); + UT_ASSERT_EQ((int)d.is_lval, 1); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_copyprop) +{ + UT_COVERS("copy_prop"); + UT_RUN(test_copyprop_var_copy_propagates_to_add); + UT_RUN(test_copyprop_tmp_copy_propagates_both_operands); + UT_RUN(test_copyprop_lval_use_preserves_deref_and_width); + UT_RUN(test_copyprop_lval_use_var_source_not_propagated); + UT_RUN(test_copyprop_lval_source_assign_not_recorded); + UT_RUN(test_copyprop_const_source_not_recorded); + UT_RUN(test_copyprop_source_redef_blocks_propagation); + UT_RUN(test_copyprop_btype_mismatch_not_recorded); + UT_RUN(test_copyprop_store_dest_tmp_source_propagates); +} diff --git a/tests/unit/arm/armv8m/test_opt_dead_lea_store.c b/tests/unit/arm/armv8m/test_opt_dead_lea_store.c new file mode 100644 index 00000000..9932fda2 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_dead_lea_store.c @@ -0,0 +1,188 @@ +/* + * test_opt_dead_lea_store.c - suite for ir/opt_dead_lea_store.c + * (dead-store elimination for LEA-deref / direct-stack STOREs) + * + * tcc_ir_opt_dead_lea_store_elim() NOPs a STORE to a local stack slot when no + * later instruction reads any byte of that slot. A slot address may appear + * directly (an lval `StackLoc[off]`) or via a single-def TEMP that holds + * `Addr[StackLoc[off]]` (the LEA-deref form produced after known_bits collapses + * bitfield chains): + * + * T1 <-- LEA Addr[StackLoc[-4]] (single-def address temp) + * T1***DEREF*** <-- val [STORE] (write through the address temp) + * + * A STORE is KEPT alive if any byte it writes is later read (a LOAD lval of the + * same slot, a temp-deref read, or a bounded mem* PARAM1). The pass also bails + * wide (returns 0, mutates nothing) when an address escapes — e.g. the address + * of a local is itself stored into memory. + * + * Notes used to build the IR (read from the pass + tccir_operand.h): + * - A LEA-temp source is a STACKOFF operand with is_local=1, is_lval=0 and + * no vreg: irop_make_stackoff(0, off, 0, 0, 0, btype) (arg-0 -> vreg -1). + * - A direct slot lval is the same with is_lval=1. + * - The pass returns 0 immediately unless there is at least one TEMP dest + * (max_tmp > 0), so every fixture defines a tracked address temp. + * + * Isolated tests: a hand-built IR sequence is run through the bare pass entry + * point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared here to avoid pulling + * in the optimizer engine headers). */ +int tcc_ir_opt_dead_lea_store_elim(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 + +/* Build a STACKOFF operand for a local slot at byte offset `off`. + * is_lval selects "the slot itself" (a memory reference) vs. "the address of the + * slot as a value" (what a LEA computes into a temp). */ +static inline IROperand utb_slot(int32_t off, int is_lval) +{ + return irop_make_stackoff(0, off, is_lval, /*is_llocal*/ 0, /*is_param*/ 0, I32); +} + +/* ------------------------------------------------------------------ tests */ + +/* POSITIVE: a STORE to a direct stack slot whose bytes are never read later is + * dead and gets NOP'd. + * + * T1 = LEA Addr[StackLoc[-8]] (single-def tracked temp; bumps max_tmp, + * never used -> stays tame) + * StackLoc[-4] <-- #7 [STORE] (dead: slot -4 is never read) -> NOP + * + * Non-vacuous: if the pass were a no-op this asserts would fail (op stays STORE, + * changes==0). */ +UT_TEST(test_dls_dead_direct_store_removed) +{ + TCCIRState *ir = utb_new(); + + /* Tracked address temp for a *different* slot so max_tmp > 0. */ + utb_emit(ir, TCCIR_OP_LEA, utb_temp(1, I32), utb_slot(-8, /*is_lval*/ 0), UTB_NONE); + int is = utb_emit(ir, TCCIR_OP_STORE, utb_slot(-4, /*is_lval*/ 1), utb_imm(7, I32), UTB_NONE); + + int changes = tcc_ir_opt_dead_lea_store_elim(ir); + + UT_ASSERT_EQ(changes, 1); + UT_ASSERT_EQ(utb_op(ir, is), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* POSITIVE: a STORE through a single-def LEA-deref address temp whose slot is + * never read later is dead and gets NOP'd. + * + * T1 = LEA Addr[StackLoc[-4]] (single-def tracked address temp) + * T1***DEREF*** <-- #7 [STORE] (dead deref store) -> NOP + * + * The STORE dest is the temp used as an lval (deref of the address it holds); + * RESOLVE_LVAL_SLOT maps it back to slot -4 via tmp_addr[]. */ +UT_TEST(test_dls_dead_lea_deref_store_removed) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_LEA, utb_temp(1, I32), utb_slot(-4, /*is_lval*/ 0), UTB_NONE); + + /* STORE dest: temp T1 used as an lval (deref). */ + IROperand deref = utb_temp(1, I32); + deref.is_lval = 1; + int is = utb_emit(ir, TCCIR_OP_STORE, deref, utb_imm(7, I32), UTB_NONE); + + int changes = tcc_ir_opt_dead_lea_store_elim(ir); + + UT_ASSERT_EQ(changes, 1); + UT_ASSERT_EQ(utb_op(ir, is), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: a STORE whose slot is read by a later LOAD is observable and must be + * KEPT. + * + * T1 = LEA Addr[StackLoc[-8]] (max_tmp bump; tame) + * StackLoc[-4] <-- #7 [STORE] (slot -4) + * T2 = LOAD StackLoc[-4] (later read of slot -4, overlapping bytes) + * + * The LOAD's lval src1 records a read at a position > the store -> alive. + * Pass returns 0 and leaves the STORE unchanged. */ +UT_TEST(test_dls_store_with_later_load_kept) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_LEA, utb_temp(1, I32), utb_slot(-8, /*is_lval*/ 0), UTB_NONE); + int is = utb_emit(ir, TCCIR_OP_STORE, utb_slot(-4, /*is_lval*/ 1), utb_imm(7, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_LOAD, utb_temp(2, I32), utb_slot(-4, /*is_lval*/ 1), UTB_NONE); + + int changes = tcc_ir_opt_dead_lea_store_elim(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, is), TCCIR_OP_STORE); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (escape bail): storing the *address* of a local into memory lets it + * escape; the pass bails wide (returns 0, mutates nothing) so it never NOPs the + * otherwise-dead-looking store. + * + * T1 = LEA Addr[StackLoc[-8]] (max_tmp bump) + * T2***DEREF*** <-- Addr[StackLoc[-4]] [STORE of an address value] + * + * The STORE's src1 is a non-lval STACKOFF (address-of-local) -> escape -> bail. + * Even though no slot is read, nothing is eliminated. */ +UT_TEST(test_dls_address_escape_bails) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_LEA, utb_temp(1, I32), utb_slot(-8, /*is_lval*/ 0), UTB_NONE); + + /* STORE dest: some deref location (temp T2 used as lval); the *value* stored + * is the address of local slot -4 (a non-lval STACKOFF) -> escaping. */ + IROperand deref = utb_temp(2, I32); + deref.is_lval = 1; + int is = utb_emit(ir, TCCIR_OP_STORE, deref, utb_slot(-4, /*is_lval*/ 0), UTB_NONE); + + int changes = tcc_ir_opt_dead_lea_store_elim(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, is), TCCIR_OP_STORE); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (no temps): with no TEMP dest in the function, max_tmp stays 0 and + * the pass returns 0 immediately without touching even a plainly dead store. + * Guards the early-out and documents the "needs a tracked temp" precondition. */ +UT_TEST(test_dls_no_temps_early_out) +{ + TCCIRState *ir = utb_new(); + + int is = utb_emit(ir, TCCIR_OP_STORE, utb_slot(-4, /*is_lval*/ 1), utb_imm(7, I32), UTB_NONE); + + int changes = tcc_ir_opt_dead_lea_store_elim(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, is), TCCIR_OP_STORE); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_dead_lea_store) +{ + UT_COVERS("dead_lea_store_elim"); + UT_RUN(test_dls_dead_direct_store_removed); + UT_RUN(test_dls_dead_lea_deref_store_removed); + UT_RUN(test_dls_store_with_later_load_kept); + UT_RUN(test_dls_address_escape_bails); + UT_RUN(test_dls_no_temps_early_out); +} diff --git a/tests/unit/arm/armv8m/test_opt_jump_thread.c b/tests/unit/arm/armv8m/test_opt_jump_thread.c new file mode 100644 index 00000000..12249cad --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_jump_thread.c @@ -0,0 +1,269 @@ +/* + * test_opt_jump_thread.c - suite for ir/opt_jump_thread.c (jump threading + + * fall-through elimination) + * + * Two entry points are exercised: + * + * tcc_ir_opt_jump_threading(): for each JUMP/JUMPIF, follows a chain of + * unconditional JUMPs (and skips NOPs) starting at the jump's target, then + * rewrites the jump's target operand to the ultimate destination. The target + * is stored in the DEST operand's 32-bit immediate (read back via + * utb_dest(ir,i).u.imm32). Guard: a conditional JUMPIF must NOT be retargeted + * BACKWARD (new_target < target) — that would land its taken edge inside an + * enclosing loop body and let downstream cleanup collapse a live loop-exit. + * + * tcc_ir_opt_eliminate_fallthrough(): rewrites to NOP any JUMP/JUMPIF whose + * target equals the next real (non-NOP) instruction — a no-op control + * transfer. For a plain JUMP this is unconditional. For a JUMPIF additional + * safety checks gate the removal (epilogue / JUMP|RETURN|TRAP successor / no + * impure CALL earlier in the basic block). + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + * + * Target encoding note: utb_imm(target_idx, I32) builds an IMM32 operand whose + * .u.imm32 == target_idx; the pass reads it via irop_get_imm64_ex() (which + * returns op.u.imm32 for IMM32) and writes the new target back into .u.imm32. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry points (defined in ir/opt_jump_thread.c; forward-declared to avoid + * pulling in the optimizer engine headers). */ +int tcc_ir_opt_jump_threading(TCCIRState *ir); +int tcc_ir_opt_eliminate_fallthrough(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 + +/* Emit a JUMP whose target index is `tgt`. */ +static int emit_jump(TCCIRState *ir, int tgt) +{ + return utb_emit(ir, TCCIR_OP_JUMP, utb_imm(tgt, I32), UTB_NONE, UTB_NONE); +} + +/* Emit a JUMPIF (conditional) with target index `tgt` and a temp condition. */ +static int emit_jumpif(TCCIRState *ir, int tgt, int cond_temp) +{ + return utb_emit(ir, TCCIR_OP_JUMPIF, utb_imm(tgt, I32), utb_temp(cond_temp, I32), UTB_NONE); +} + +/* Read a jump's current target index. */ +static int jump_target(TCCIRState *ir, int i) +{ + return (int)utb_dest(ir, i).u.imm32; +} + +/* ------------------------------------------------------- jump_threading tests */ + +/* JUMP -> JUMP chain collapse (POSITIVE): + * 0: JUMP -> 1 + * 1: JUMP -> 2 + * 2: ADD (real instruction = final target) + * Following the unconditional-jump chain from target 1 reaches the real ADD at + * index 2, so jump 0's target must be rewritten 1 -> 2. Would FAIL (stay 1) if + * the chain were not followed. */ +UT_TEST(test_jt_chain_collapses_to_final_target) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 1); + emit_jump(ir, 2); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_jump_threading(ir); + + UT_ASSERT(changes >= 1); + UT_ASSERT_EQ(utb_op(ir, j0), TCCIR_OP_JUMP); /* still a JUMP, just retargeted */ + UT_ASSERT_EQ(jump_target(ir, j0), 2); /* threaded past the middle JUMP */ + + utb_free(ir); + return 0; +} + +/* JUMP through NOPs (POSITIVE): + * 0: JUMP -> 1 + * 1: NOP + * 2: NOP + * 3: ADD + * follow_jump_chain skips the NOPs at the target and find_first_non_nop lands on + * the ADD at 3, so jump 0's target is rewritten 1 -> 3. */ +UT_TEST(test_jt_skips_nops_to_real_instruction) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 1); + utb_emit(ir, TCCIR_OP_NOP, UTB_NONE, UTB_NONE, UTB_NONE); + utb_emit(ir, TCCIR_OP_NOP, UTB_NONE, UTB_NONE, UTB_NONE); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_jump_threading(ir); + + UT_ASSERT(changes >= 1); + UT_ASSERT_EQ(jump_target(ir, j0), 3); + + utb_free(ir); + return 0; +} + +/* JUMP already pointing at a real instruction (NEGATIVE / no-op): + * 0: JUMP -> 1 + * 1: ADD + * Target 1 is already a non-jump, non-NOP instruction, so nothing to thread. */ +UT_TEST(test_jt_direct_target_no_change) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 1); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_jump_threading(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(jump_target(ir, j0), 1); + + utb_free(ir); + return 0; +} + +/* Conditional backward-threading guard (NEGATIVE for JUMPIF): + * 0: ADD (real instruction, would be the chased target) + * 1: JUMP -> 0 (unconditional back-edge to 0) + * 2: JUMPIF -> 1 (conditional; chasing the chain at 1 would reach 0, BACKWARD) + * follow_jump_chain(1) -> 0, which is < target(1). Because instr 2 is a JUMPIF + * and new_target(0) < target(1), the pass must REVERT the conditional target to + * 1 (no backward conditional threading), leaving JUMPIF 2 unchanged. + * + * The unconditional JUMP at 1 is NOT subject to the guard and may be threaded + * (target 0 is already a real instruction, so it stays 0 here). */ +UT_TEST(test_jt_conditional_backward_guard) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + emit_jump(ir, 0); + int jif = emit_jumpif(ir, 1, 0); + + tcc_ir_opt_jump_threading(ir); + + /* The conditional jump's target must remain 1 (guard prevents backward + * retarget to 0). */ + UT_ASSERT_EQ(utb_op(ir, jif), TCCIR_OP_JUMPIF); + UT_ASSERT_EQ(jump_target(ir, jif), 1); + + utb_free(ir); + return 0; +} + +/* --------------------------------------------------- eliminate_fallthrough */ + +/* Unconditional JUMP to the next instruction (POSITIVE): + * 0: JUMP -> 1 + * 1: ADD + * next_real after index 0 is 1, which equals the target -> the JUMP is a pure + * no-op and must be rewritten to NOP; return >= 1. */ +UT_TEST(test_ef_jump_to_next_becomes_nop) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 1); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_eliminate_fallthrough(ir); + + UT_ASSERT(changes >= 1); + UT_ASSERT_EQ(utb_op(ir, j0), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* Fall-through across NOPs (POSITIVE): + * 0: JUMP -> 2 + * 1: NOP + * 2: ADD + * find_first_non_nop(1) skips the NOP and returns 2, which equals the target, + * so the JUMP is still a no-op fall-through and is eliminated. */ +UT_TEST(test_ef_jump_to_next_across_nop_becomes_nop) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 2); + utb_emit(ir, TCCIR_OP_NOP, UTB_NONE, UTB_NONE, UTB_NONE); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_eliminate_fallthrough(ir); + + UT_ASSERT(changes >= 1); + UT_ASSERT_EQ(utb_op(ir, j0), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* Conditional JUMPIF fall-through (POSITIVE, safe path): + * 0: JUMPIF -> 1 + * 1: ADD + * target(1) == next_real(1). Safety: next_real=1 < n and instr 1 is ADD (not a + * JUMP/RETURN/TRAP), so case (a) does not fire; the backward CALL scan finds no + * prior instructions (j starts at -1) -> safe. The JUMPIF is eliminated to NOP. */ +UT_TEST(test_ef_jumpif_to_next_safe_becomes_nop) +{ + TCCIRState *ir = utb_new(); + + int jif = emit_jumpif(ir, 1, 0); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_imm(1, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_eliminate_fallthrough(ir); + + UT_ASSERT(changes >= 1); + UT_ASSERT_EQ(utb_op(ir, jif), TCCIR_OP_NOP); + + utb_free(ir); + return 0; +} + +/* Real (non-fall-through) jump must be preserved (NEGATIVE): + * 0: JUMP -> 2 + * 1: ADD (next real after 0) + * 2: SUB + * next_real after 0 is 1, but the target is 2 -> not a fall-through, so the JUMP + * is a genuine branch and must NOT be eliminated. */ +UT_TEST(test_ef_real_branch_preserved) +{ + TCCIRState *ir = utb_new(); + + int j0 = emit_jump(ir, 2); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(0, I32), utb_imm(1, I32), utb_imm(2, I32)); + utb_emit(ir, TCCIR_OP_SUB, utb_temp(1, I32), utb_imm(5, I32), utb_imm(2, I32)); + + int changes = tcc_ir_opt_eliminate_fallthrough(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, j0), TCCIR_OP_JUMP); + UT_ASSERT_EQ(jump_target(ir, j0), 2); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_jump_thread) +{ + UT_COVERS("jump_threading"); + UT_COVERS("eliminate_fallthrough"); + + /* jump_threading */ + UT_RUN(test_jt_chain_collapses_to_final_target); + UT_RUN(test_jt_skips_nops_to_real_instruction); + UT_RUN(test_jt_direct_target_no_change); + UT_RUN(test_jt_conditional_backward_guard); + + /* eliminate_fallthrough */ + UT_RUN(test_ef_jump_to_next_becomes_nop); + UT_RUN(test_ef_jump_to_next_across_nop_becomes_nop); + UT_RUN(test_ef_jumpif_to_next_safe_becomes_nop); + UT_RUN(test_ef_real_branch_preserved); +} diff --git a/tests/unit/arm/armv8m/test_opt_knownbits.c b/tests/unit/arm/armv8m/test_opt_knownbits.c new file mode 100644 index 00000000..85fc72de --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_knownbits.c @@ -0,0 +1,242 @@ +/* + * test_opt_knownbits.c - suite for ir/opt_knownbits.c (known-bits propagation) + * + * tcc_ir_opt_known_bits tracks, per TEMP and per stack slot, which bits are + * statically known to be 0 or 1 (a kz/ko lattice over 32 bits, single-BB + * scope). When every bit of a TEMP destination becomes known, the defining + * op is rewritten to an immediate ASSIGN; it also folds constant stack-slot + * reads, narrow LOADs (honoring the load width + signed/unsigned extension), + * and a few branch/SETIF patterns. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + * + * Covered: + * (a) POSITIVE folds the pass really performs (assert rewritten op + the + * exact folded immediate + changes > 0): + * - AND with #0 -> ASSIGN #0 (all bits forced to 0) + * - OR with #-1 -> ASSIGN #-1 (all bits forced to 1) + * - (param OR #0xFF) SHL #24 -> ASSIGN #0xFF000000 (bitfield-style: + * low byte forced to ones, shift makes the whole word known) + * (b) Narrow-width LOAD is honored (HISTORICAL BUG guard): a value stored + * 32-bit wide and read back through a sub-word LOAD must be masked to + * the load width and (zero/sign)-extended per dest.is_unsigned, never + * carrying the dropped upper bytes. + * (c) NEGATIVE: when operands carry no known bits, nothing folds and the + * instruction is left unchanged with changes == 0. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared here to avoid + * pulling in the optimizer engine headers). */ +int tcc_ir_opt_known_bits(TCCIRState *ir); + +#define I8 IROP_BTYPE_INT8 +#define I32 IROP_BTYPE_INT32 + +/* Build a direct StackLoc[off] lvalue operand (is_lval=1, no vreg) that the + * pass recognizes via kb_is_direct_stackoff(). */ +static IROperand kb_stack_lval(int32_t off, int btype) +{ + return irop_make_stackoff(-1, off, /*is_lval*/1, /*is_llocal*/0, + /*is_param*/0, btype); +} + +/* ------------------------------------------------------------------ tests */ + +/* T1 = param0 AND #0 + * param0 carries no known bits, but AND #0 forces every result bit to 0, so + * known-bits proves the whole destination is 0 and rewrites the AND into an + * immediate ASSIGN #0. (Pos 1 so max_tmp_pos > 0 and the pass runs.) */ +UT_TEST(test_knownbits_and_zero_folds) +{ + TCCIRState *ir = utb_new(); + + int i0 = utb_emit(ir, TCCIR_OP_AND, utb_temp(1, I32), + utb_param(0, I32), utb_imm(0, I32)); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, i0), TCCIR_OP_ASSIGN); + UT_ASSERT(irop_is_immediate(utb_src1(ir, i0))); + UT_ASSERT_EQ(irop_get_imm64_ex(ir, utb_src1(ir, i0)), 0); + + utb_free(ir); + return 0; +} + +/* T1 = param0 OR #-1 + * OR with all-ones forces every result bit to 1 regardless of param0, so the + * destination is fully known (0xFFFFFFFF) and the OR folds to ASSIGN #-1. */ +UT_TEST(test_knownbits_or_allones_folds) +{ + TCCIRState *ir = utb_new(); + + int i0 = utb_emit(ir, TCCIR_OP_OR, utb_temp(1, I32), + utb_param(0, I32), utb_imm(-1, I32)); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, i0), TCCIR_OP_ASSIGN); + UT_ASSERT(irop_is_immediate(utb_src1(ir, i0))); + UT_ASSERT_EQ(irop_get_imm64_ex(ir, utb_src1(ir, i0)), -1); + + utb_free(ir); + return 0; +} + +/* Bitfield-style positive: the low byte is forced to ones, then shifted to the + * top of the word, leaving every bit determined. + * T1 = param0 OR #0xFF ; low 8 bits known-one, high 24 unknown + * T2 = T1 SHL #24 ; SHL injects 24 known-zero low bits and shifts + * the known-one byte up -> whole word known + * -> T2 folds to ASSIGN #0xFF000000. + * Only the SHL is a full-word fold; the OR is left as-is (high bits unknown), + * so exactly one rewrite happens. */ +UT_TEST(test_knownbits_or_then_shl_folds_word) +{ + TCCIRState *ir = utb_new(); + + int i_or = utb_emit(ir, TCCIR_OP_OR, utb_temp(1, I32), + utb_param(0, I32), utb_imm(0xFF, I32)); + int i_shl = utb_emit(ir, TCCIR_OP_SHL, utb_temp(2, I32), + utb_temp(1, I32), utb_imm(24, I32)); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT(changes > 0); + /* OR's high bits stay unknown -> not folded. */ + UT_ASSERT_EQ(utb_op(ir, i_or), TCCIR_OP_OR); + /* SHL becomes a full-word immediate ASSIGN. */ + UT_ASSERT_EQ(utb_op(ir, i_shl), TCCIR_OP_ASSIGN); + UT_ASSERT(irop_is_immediate(utb_src1(ir, i_shl))); + /* 0xFF000000 read back as a sign-extended 32-bit immediate. */ + UT_ASSERT_EQ((int32_t)irop_get_imm64_ex(ir, utb_src1(ir, i_shl)), + (int32_t)0xFF000000); + + utb_free(ir); + return 0; +} + +/* HISTORICAL BUG guard - narrow unsigned LOAD must honor the load width. + * *(StackLoc[-4]) = #0x000001F2 ; store a full 32-bit value + * T1 = (uint8_t) LOAD StackLoc[-4]; read back as an UNSIGNED byte + * The slot's known value is 0x1F2, but the byte load sees only 0xF2 with the + * upper bytes zero-extended. The fold must produce 0xF2 (242), NOT 0x1F2 and + * NOT a sign-extended value: the dropped upper byte must not leak into the + * known bits. (Low byte 0xF2 != 0xFF, so the all-ones-byte rewrite-suppression + * does not apply and the LOAD is rewritten to ASSIGN.) */ +UT_TEST(test_knownbits_narrow_unsigned_load_masks_width) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_STORE, kb_stack_lval(-4, I32), utb_imm(0x1F2, I32), + UTB_NONE); + + /* Destination and the byte-load source are both unsigned 8-bit: the slot + * read goes through the constant-stack-slot fold (kb_apply_const_width), + * which reads the SOURCE operand's is_unsigned, while the kb path reads the + * dest's — mark both so either fold path zero-extends. */ + IROperand dst = utb_temp(1, I8); + dst.is_unsigned = 1; + IROperand src = kb_stack_lval(-4, I8); + src.is_unsigned = 1; + int i_ld = utb_emit(ir, TCCIR_OP_LOAD, dst, src, UTB_NONE); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, i_ld), TCCIR_OP_ASSIGN); + UT_ASSERT(irop_is_immediate(utb_src1(ir, i_ld))); + /* Exactly the low byte, zero-extended: 0xF2 == 242, not 0x1F2 (498). */ + UT_ASSERT_EQ(irop_get_imm64_ex(ir, utb_src1(ir, i_ld)), 0xF2); + + utb_free(ir); + return 0; +} + +/* Companion to the width guard - narrow SIGNED LOAD sign-extends. + * *(StackLoc[-8]) = #0x80 ; low byte 0x80, bit 7 set + * T1 = (int8_t) LOAD StackLoc[-8] ; signed byte load + * A signed byte load of 0x80 must sign-extend to 0xFFFFFF80 == -128, exercising + * the signed branch of kb_apply_load_width (sign bit known -> upper bytes + * known-one), distinct from the zero-extend above. */ +UT_TEST(test_knownbits_narrow_signed_load_sign_extends) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_STORE, kb_stack_lval(-8, I32), utb_imm(0x80, I32), + UTB_NONE); + + IROperand dst = utb_temp(1, I8); /* signed: is_unsigned stays 0 */ + int i_ld = utb_emit(ir, TCCIR_OP_LOAD, dst, kb_stack_lval(-8, I8), UTB_NONE); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT(changes > 0); + UT_ASSERT_EQ(utb_op(ir, i_ld), TCCIR_OP_ASSIGN); + UT_ASSERT(irop_is_immediate(utb_src1(ir, i_ld))); + UT_ASSERT_EQ((int32_t)irop_get_imm64_ex(ir, utb_src1(ir, i_ld)), -128); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: both operands are unknown params, so no result bit is determined. + * AND of two unknowns yields no known bits -> the pass must NOT fold and must + * report zero changes, leaving the AND intact. */ +UT_TEST(test_knownbits_unknown_operands_no_fold) +{ + TCCIRState *ir = utb_new(); + + int i0 = utb_emit(ir, TCCIR_OP_AND, utb_temp(1, I32), + utb_param(0, I32), utb_param(1, I32)); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i0), TCCIR_OP_AND); + + utb_free(ir); + return 0; +} + +/* NEGATIVE: a partially-known value is not fully determined, so it is not + * folded to a constant. + * T1 = param0 OR #0xFF ; low byte known-one, high 24 bits unknown + * The OR records kb but, because the destination is not fully known, must be + * left as an OR (not rewritten to ASSIGN) and contribute no change. */ +UT_TEST(test_knownbits_partial_known_no_fold) +{ + TCCIRState *ir = utb_new(); + + int i0 = utb_emit(ir, TCCIR_OP_OR, utb_temp(1, I32), + utb_param(0, I32), utb_imm(0xFF, I32)); + + int changes = tcc_ir_opt_known_bits(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i0), TCCIR_OP_OR); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_knownbits) +{ + UT_COVERS("known_bits"); + UT_RUN(test_knownbits_and_zero_folds); + UT_RUN(test_knownbits_or_allones_folds); + UT_RUN(test_knownbits_or_then_shl_folds_word); + UT_RUN(test_knownbits_narrow_unsigned_load_masks_width); + UT_RUN(test_knownbits_narrow_signed_load_sign_extends); + UT_RUN(test_knownbits_unknown_operands_no_fold); + UT_RUN(test_knownbits_partial_known_no_fold); +} diff --git a/tests/unit/arm/armv8m/test_opt_licm.c b/tests/unit/arm/armv8m/test_opt_licm.c new file mode 100644 index 00000000..bd8ad4ba --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_licm.c @@ -0,0 +1,276 @@ +/* + * test_opt_licm.c - suite for ir/licm.c (loop-invariant code motion) + * + * tcc_ir_opt_licm() runs the dominance-based LICM in tcc_ir_opt_licm_ex(): + * 1. tcc_ir_cfg_build() splits compact_instructions[] into basic blocks at + * jump targets / fall-through-after-jump boundaries. + * 2. compute dominators, find natural loops via dominance-verified back-edges + * (an edge b->h where h dominates b). + * 3. for each loop with a valid preheader (a unique out-of-loop predecessor + * of the header that ALSO dominates the header), mark side-effect-free + * arithmetic/assign whose operands are all loop-invariant, and hoist a + * CLONE of each such instruction into the preheader, NOP-ing the original. + * + * Return value note: tcc_ir_opt_licm() returns loops->num_loops (the count of + * detected loops), NOT the count of hoisted instructions. So a non-zero return + * means "a loop was found", not "the IR was rewritten". To assert a real hoist + * we therefore also check the instruction stream directly: a hoist INSERTS one + * instruction at the preheader (next_instruction_index grows by 1) and NOPs the + * original in-loop copy. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + * + * Building a loop the pass will actually transform requires a real back-edge: + * a preheader block that dominates the header, the header itself (target of a + * conditional back-edge), an invariant computation, and a JUMPIF latch whose + * dest immediate is the header index. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h / licm.h; forward-declared to avoid + * pulling in the optimizer engine headers). */ +int tcc_ir_opt_licm(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 + +/* utb_new() leaves iroperand_pool_capacity / compact_instructions_size at 0 + * (it pre-fills the buffers but not the capacity bookkeeping). LICM hoisting + * calls tcc_ir_pool_add() and insert_instruction_before(), both of which grow + * via those fields. Set them to the real allocated sizes so the existing + * UTB_MAX_* buffers are used in place (our sequences are tiny, well under the + * limits, so no reallocation is triggered). */ +static TCCIRState *utb_loop_new(void) +{ + TCCIRState *ir = utb_new(); + ir->iroperand_pool_capacity = UTB_MAX_OPERANDS; + ir->compact_instructions_size = UTB_MAX_INSTR; + return ir; +} + +/* Build a JUMP/JUMPIF target operand the way licm/cfg decode it: + * irop_make_imm32(-1, target, INT32) -> no vreg, imm32 = instruction index. */ +static IROperand utb_jtarget(int target) +{ + return irop_make_imm32(-1, target, I32); +} + +/* Count NOP instructions in [0, next_instruction_index). */ +static int count_nops(TCCIRState *ir) +{ + int n = 0; + for (int i = 0; i < ir->next_instruction_index; i++) + if (ir->compact_instructions[i].op == TCCIR_OP_NOP) + n++; + return n; +} + +/* Find the first instruction with the given op whose dest vreg matches `vreg`. + * Returns its index, or -1. */ +static int find_def(TCCIRState *ir, TccIrOp op, int vreg) +{ + for (int i = 0; i < ir->next_instruction_index; i++) + { + IRQuadCompact *q = &ir->compact_instructions[i]; + if (q->op != op) + continue; + if (!irop_config[op].has_dest) + continue; + if (utb_vreg(tcc_ir_op_get_dest(ir, q)) == vreg) + return i; + } + return -1; +} + +/* ------------------------------------------------------------------ tests */ + +/* POSITIVE: a real natural loop with a loop-invariant ADD that must be hoisted. + * + * idx 0: T0 = #100 ; preheader (block 0, dominates header) + * idx 1: T1 = T0 + #5 ; loop header (block 1) -- INVARIANT + * idx 2: T2 = T2 + #1 ; loop body -- varying (self def) + * idx 3: JUMPIF ->1 (cond T3) ; latch / conditional back-edge to header + * idx 4: RETURNVOID ; exit (block 2) + * + * Block 0 = {0}, block 1 = {1,2,3} (header=1, latch=3), block 2 = {4}. + * back-edge block1->block1 with header dominating latch => natural loop. + * preheader = block 0 (unique out-of-loop pred of header, dominates it). + * T1 = T0 + #5 is invariant (T0 defined outside loop, #5 const, single def), + * its block (1) dominates the only exit block (1) => SAFE to hoist. + * + * Effect: a clone of `T1 = T0 + #5` is inserted at the preheader insert point + * (index 1), the original is NOP'd, instruction count grows by 1, and the + * JUMPIF target (was 1) is bumped to 2 by insert_instruction_before. */ +UT_TEST(test_licm_hoists_invariant_add) +{ + TCCIRState *ir = utb_loop_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(100, I32), UTB_NONE); /* 0 */ + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(5, I32));/* 1 header, invariant */ + utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(2, I32), utb_imm(1, I32));/* 2 varying */ + utb_emit(ir, TCCIR_OP_JUMPIF, utb_jtarget(1), utb_temp(3, I32), UTB_NONE); /* 3 back-edge */ + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); /* 4 exit */ + + int n_before = ir->next_instruction_index; + int nops_before = count_nops(ir); + + int loops = tcc_ir_opt_licm(ir); + + /* A loop was detected (return value is the loop count, not the hoist count). */ + UT_ASSERT(loops >= 1); + + /* The hoist inserted exactly one instruction at the preheader. */ + UT_ASSERT_EQ(ir->next_instruction_index, n_before + 1); + + /* ...and NOP'd the original in-loop copy: exactly one new NOP appeared. */ + UT_ASSERT_EQ(count_nops(ir), nops_before + 1); + + /* The hoisted ADD that defines T1 must now live BEFORE the loop header. + * The original header was at index 1; after inserting one instruction at the + * preheader (index 1), the hoisted ADD sits at index 1 and the (now-NOP'd) + * loop body starts at index 2. The live ADD defining T1 is the hoisted one. */ + int t1_def = find_def(ir, TCCIR_OP_ADD, TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 1)); + UT_ASSERT(t1_def >= 0); + /* It is the hoisted copy at the preheader insert position (index 1), which is + * before the back-edge JUMPIF (now at index 4). */ + UT_ASSERT_EQ(t1_def, 1); + UT_ASSERT_EQ(utb_op(ir, t1_def), TCCIR_OP_ADD); + UT_ASSERT_EQ(utb_vreg(tcc_ir_op_get_src1(ir, &ir->compact_instructions[t1_def])), + TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 0)); + + /* The back-edge JUMPIF target was rewritten from 1 to 2 (header shifted by + * the inserted preheader instruction). */ + int jmp_idx = -1; + for (int i = 0; i < ir->next_instruction_index; i++) + if (ir->compact_instructions[i].op == TCCIR_OP_JUMPIF) + { + jmp_idx = i; + break; + } + UT_ASSERT(jmp_idx >= 0); + { + IROperand dest = tcc_ir_op_get_dest(ir, &ir->compact_instructions[jmp_idx]); + UT_ASSERT_EQ((int)irop_get_imm64_ex(ir, dest), 2); + } + + utb_free(ir); + return 0; +} + +/* NEGATIVE (no loop): a straight-line sequence has no back-edge, so no loop is + * detected, nothing is hoisted, and the IR is left byte-for-byte intact. */ +UT_TEST(test_licm_no_loop_no_change) +{ + TCCIRState *ir = utb_loop_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(100, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(0, I32), utb_imm(5, I32)); + utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(1, I32), utb_imm(1, I32)); + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); + + int n_before = ir->next_instruction_index; + int nops_before = count_nops(ir); + + int loops = tcc_ir_opt_licm(ir); + + /* No back-edge => no loop detected => return 0, IR unchanged. */ + UT_ASSERT_EQ(loops, 0); + UT_ASSERT_EQ(ir->next_instruction_index, n_before); + UT_ASSERT_EQ(count_nops(ir), nops_before); + UT_ASSERT_EQ(utb_op(ir, 1), TCCIR_OP_ADD); + UT_ASSERT_EQ(utb_op(ir, 2), TCCIR_OP_ADD); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (loop, but nothing invariant): a loop whose only body computation is + * a self-referencing accumulator (T1 = T1 + #1) has no hoistable instruction. + * A loop IS detected (non-zero return), but the IR must NOT grow and no NOP must + * appear (nothing was hoisted/replaced). + * + * idx 0: T0 = #0 ; preheader (defines accumulator seed... outside loop) + * idx 1: T1 = T1 + #1 ; header -- VARYING (dest also a source, self def) + * idx 2: JUMPIF ->1 (T2) ; back-edge + * idx 3: RETURNVOID ; exit + */ +UT_TEST(test_licm_loop_no_invariant_no_hoist) +{ + TCCIRState *ir = utb_loop_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(0, I32), UTB_NONE); /* 0 preheader */ + utb_emit(ir, TCCIR_OP_ADD, utb_temp(1, I32), utb_temp(1, I32), utb_imm(1, I32));/* 1 header varying */ + utb_emit(ir, TCCIR_OP_JUMPIF, utb_jtarget(1), utb_temp(2, I32), UTB_NONE); /* 2 back-edge */ + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); /* 3 exit */ + + int n_before = ir->next_instruction_index; + int nops_before = count_nops(ir); + + int loops = tcc_ir_opt_licm(ir); + + /* Loop detected, but nothing invariant -> no instruction inserted, no NOP. */ + UT_ASSERT(loops >= 1); + UT_ASSERT_EQ(ir->next_instruction_index, n_before); + UT_ASSERT_EQ(count_nops(ir), nops_before); + /* The self-referencing accumulator is left in place. */ + UT_ASSERT_EQ(utb_op(ir, 1), TCCIR_OP_ADD); + UT_ASSERT_EQ(utb_vreg(utb_dest(ir, 1)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 1)); + + utb_free(ir); + return 0; +} + +/* NEGATIVE (guard): an instruction whose source is a memory dereference (lvalue) + * must NOT be hoisted even though it looks invariant, because it may read + * volatile / changing memory. Here `T1 = LOAD [T0(lval)]` where T0 is defined + * outside the loop -- T0 is loop-invariant but the LOAD's src is a deref, so the + * has_deref guard in dom-LICM blocks the hoist. + * + * idx 0: T0 = #100 ; preheader + * idx 1: T1 = LOAD [T0]lval ; header -- deref source, NOT hoistable + * idx 2: T2 = T2 + #1 ; varying + * idx 3: JUMPIF ->1 (T3) ; back-edge + * idx 4: RETURNVOID ; exit + */ +UT_TEST(test_licm_deref_source_not_hoisted) +{ + TCCIRState *ir = utb_loop_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(100, I32), UTB_NONE); /* 0 */ + /* LOAD dest=T1, src1 = T0 marked as lvalue (deref). */ + IROperand load_src = utb_temp(0, I32); + load_src.is_lval = 1; + utb_emit(ir, TCCIR_OP_LOAD, utb_temp(1, I32), load_src, UTB_NONE); /* 1 deref */ + utb_emit(ir, TCCIR_OP_ADD, utb_temp(2, I32), utb_temp(2, I32), utb_imm(1, I32));/* 2 varying */ + utb_emit(ir, TCCIR_OP_JUMPIF, utb_jtarget(1), utb_temp(3, I32), UTB_NONE); /* 3 back-edge */ + utb_emit(ir, TCCIR_OP_RETURNVOID, UTB_NONE, UTB_NONE, UTB_NONE); /* 4 exit */ + + int n_before = ir->next_instruction_index; + int nops_before = count_nops(ir); + + int loops = tcc_ir_opt_licm(ir); + + /* Loop detected, but the LOAD has a deref source -> not hoisted. LOAD is also + * not in the hoistable opcode set at all, so doubly guarded. */ + UT_ASSERT(loops >= 1); + UT_ASSERT_EQ(ir->next_instruction_index, n_before); + UT_ASSERT_EQ(count_nops(ir), nops_before); + UT_ASSERT_EQ(utb_op(ir, 1), TCCIR_OP_LOAD); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_licm) +{ + UT_COVERS("licm"); + UT_RUN(test_licm_hoists_invariant_add); + UT_RUN(test_licm_no_loop_no_change); + UT_RUN(test_licm_loop_no_invariant_no_hoist); + UT_RUN(test_licm_deref_source_not_hoisted); +} diff --git a/tests/unit/arm/armv8m/test_opt_neg_chain.c b/tests/unit/arm/armv8m/test_opt_neg_chain.c new file mode 100644 index 00000000..286ab358 --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_neg_chain.c @@ -0,0 +1,114 @@ +/* + * test_opt_neg_chain.c - suite for ir/opt_neg_chain.c (negation-chain CSE) + * + * tcc_ir_opt_neg_chain_cse tracks each TEMP as a canonical (base, sign) pair + * (sign = parity of accumulated negations). When `T_b = #0 SUB T_a` recomputes + * a (base, sign) already produced by an earlier TEMP T_y, the SUB is rewritten + * as `T_b = T_y` (ASSIGN), to be collapsed by a later copy-prop + DCE. + * + * These are isolated tests: a hand-built IR sequence is run through the bare + * pass entry point and the resulting instructions are inspected directly. + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared to avoid pulling in + * the optimizer engine headers). */ +int tcc_ir_opt_neg_chain_cse(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 +#define I64 IROP_BTYPE_INT64 + +/* ------------------------------------------------------------------ tests */ + +/* T0 = 5 (anchor) + * T1 = -T0 (first negation of T0) + * T2 = -T1 == T0 -> folds to T2 = T0 (ASSIGN), because the canonical + * (base=T0, sign=+) was already produced by the anchor. */ +UT_TEST(test_neg_chain_double_negation_folds) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_SUB, utb_temp(1, I32), utb_imm(0, I32), utb_temp(0, I32)); + int i2 = utb_emit(ir, TCCIR_OP_SUB, utb_temp(2, I32), utb_imm(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_neg_chain_cse(ir); + + UT_ASSERT_EQ(changes, 1); + UT_ASSERT_EQ(utb_op(ir, i2), TCCIR_OP_ASSIGN); + UT_ASSERT_EQ(utb_vreg(utb_src1(ir, i2)), TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 0)); + + utb_free(ir); + return 0; +} + +/* A single negation has nothing to CSE against -> no change, SUB preserved. */ +UT_TEST(test_neg_chain_single_negation_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(5, I32), UTB_NONE); + int i1 = utb_emit(ir, TCCIR_OP_SUB, utb_temp(1, I32), utb_imm(0, I32), utb_temp(0, I32)); + + int changes = tcc_ir_opt_neg_chain_cse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i1), TCCIR_OP_SUB); + + utb_free(ir); + return 0; +} + +/* `T_b = imm - T_a` with imm != 0 is plain subtraction, not negation -> no fold, + * even when it forms a chain that would otherwise be canonicalizable. */ +UT_TEST(test_neg_chain_nonzero_minuend_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_SUB, utb_temp(1, I32), utb_imm(7, I32), utb_temp(0, I32)); + int i2 = utb_emit(ir, TCCIR_OP_SUB, utb_temp(2, I32), utb_imm(7, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_neg_chain_cse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i2), TCCIR_OP_SUB); + + utb_free(ir); + return 0; +} + +/* Width guard: the canonical match exists, but the final SUB's dest width + * differs from the negated source width, so folding it to an ASSIGN could + * drop/extend bits the SUB wouldn't have -> the pass must NOT fold. */ +UT_TEST(test_neg_chain_width_mismatch_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_SUB, utb_temp(1, I32), utb_imm(0, I32), utb_temp(0, I32)); + /* dest T2 is 64-bit while src2 T1 is 32-bit -> dest_btype != src_btype. */ + int i2 = utb_emit(ir, TCCIR_OP_SUB, utb_temp(2, I64), utb_imm(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_neg_chain_cse(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, i2), TCCIR_OP_SUB); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_neg_chain) +{ + UT_COVERS("neg_chain_cse"); + UT_RUN(test_neg_chain_double_negation_folds); + UT_RUN(test_neg_chain_single_negation_no_fold); + UT_RUN(test_neg_chain_nonzero_minuend_no_fold); + UT_RUN(test_neg_chain_width_mismatch_no_fold); +} diff --git a/tests/unit/arm/armv8m/test_opt_setif_or_taut.c b/tests/unit/arm/armv8m/test_opt_setif_or_taut.c new file mode 100644 index 00000000..05ffd57b --- /dev/null +++ b/tests/unit/arm/armv8m/test_opt_setif_or_taut.c @@ -0,0 +1,197 @@ +/* + * test_opt_setif_or_taut.c - suite for ir/opt_setif_or_taut.c + * (SETIF OR-chain tautology fold) + * + * tcc_ir_opt_setif_or_tautology recognizes bitwise-OR chains over CMP+SETIF + * booleans that all compare the *same* operands. Each comparison token is + * mapped to a 3-bit cover mask over the integer-compare outcomes + * {LT=bit0, EQ=bit1, GT=bit2} via cond_to_mask(). An `OR Td = Ta | Tb` + * whose two SETIF sources were recorded for a compatible compare context + * combines their masks; when the union reaches 0b111 (covers LT, EQ and GT) + * the OR is provably always 1 and the instruction is rewritten in place to + * `ASSIGN Td = #1`. The pass returns the number of such folds. + * + * How the pass reads the pattern (mirrored exactly by these hand-built IRs): + * - SETIF (config {dest, src1}): dest is the boolean TEMP; src1 is an + * immediate holding the comparison token (vtop->cmp_op, e.g. TOK_LT). + * - The CMP that feeds a SETIF is the most-recent non-NOP instruction + * *immediately before* the SETIF; its src1/src2 are snapshotted as the + * compare context (vreg or immediate, signed vs unsigned). + * - Two SETIF booleans are "compatible" only within the same basic block, + * same signedness, and identical compare operands. + * + * Isolated tests: a tiny IR sequence is run through the bare pass entry point + * and the resulting instructions are inspected directly (no QEMU / frontend). + */ + +#include "ir_build.h" + +#include "ut.h" + +/* Pass entry point (declared in ir/opt.h; forward-declared here to avoid + * pulling in the optimizer-engine headers). */ +int tcc_ir_opt_setif_or_tautology(TCCIRState *ir); + +#define I32 IROP_BTYPE_INT32 + +/* ------------------------------------------------------------------ tests */ + +/* Minimal tautology: (a < 0) | (a >= 0). + * + * i0: CMP a, #0 + * i1: SETIF T0, #TOK_LT -> mask LT = 0b001 + * i2: CMP a, #0 + * i3: SETIF T1, #TOK_GE -> mask GE = 0b110 + * i4: OR T2 = T0 | T1 -> combined = 0b111 => ASSIGN T2 = #1 + * + * LT and GE together cover all three compare outcomes, so the OR is always 1. + * Positive / non-vacuous: would FAIL if the pass were a no-op. */ +UT_TEST(test_setif_or_lt_ge_covers_all_folds_to_one) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(0, I32), utb_imm(TOK_LT, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(1, I32), utb_imm(TOK_GE, I32), UTB_NONE); + int ior = utb_emit(ir, TCCIR_OP_OR, utb_temp(2, I32), + utb_temp(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_setif_or_tautology(ir); + + UT_ASSERT_EQ(changes, 1); + /* OR rewritten to ASSIGN T2 = #1. */ + UT_ASSERT_EQ(utb_op(ir, ior), TCCIR_OP_ASSIGN); + IROperand s1 = utb_src1(ir, ior); + UT_ASSERT(irop_is_immediate(s1)); + UT_ASSERT_EQ(irop_get_imm64_ex(ir, s1), 1); + /* dest TEMP untouched. */ + UT_ASSERT_EQ(utb_vreg(utb_dest(ir, ior)), + TCCIR_ENCODE_VREG(TCCIR_VREG_TYPE_TEMP, 2)); + + utb_free(ir); + return 0; +} + +/* The sc.c torture pattern collapsed: (a==0) | (a!=0). + * + * EQ mask = 0b010, NE mask = 0b101 -> union = 0b111 => fold to #1. + * + * A second positive proving the EQ/NE pairing (single OR) also triggers. */ +UT_TEST(test_setif_or_eq_ne_covers_all_folds_to_one) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(0, I32), utb_imm(TOK_EQ, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(1, I32), utb_imm(TOK_NE, I32), UTB_NONE); + int ior = utb_emit(ir, TCCIR_OP_OR, utb_temp(2, I32), + utb_temp(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_setif_or_tautology(ir); + + UT_ASSERT_EQ(changes, 1); + UT_ASSERT_EQ(utb_op(ir, ior), TCCIR_OP_ASSIGN); + UT_ASSERT_EQ(irop_get_imm64_ex(ir, utb_src1(ir, ior)), 1); + + utb_free(ir); + return 0; +} + +/* Non-tautological: (a < 0) | (a == 0) == (a <= 0). + * + * LT mask = 0b001, EQ mask = 0b010 -> union = 0b011 != 0b111. + * + * The GT outcome is NOT covered, so the OR is a genuine boolean computation + * and must be left unchanged. Negative test: returns 0, OR preserved. */ +UT_TEST(test_setif_or_lt_eq_partial_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(0, I32), utb_imm(TOK_LT, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(1, I32), utb_imm(TOK_EQ, I32), UTB_NONE); + int ior = utb_emit(ir, TCCIR_OP_OR, utb_temp(2, I32), + utb_temp(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_setif_or_tautology(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, ior), TCCIR_OP_OR); + + utb_free(ir); + return 0; +} + +/* Operand-mismatch guard: masks DO union to 0b111, but the two SETIFs compare + * different variables, so they are not the same boolean predicate and the OR + * is not a tautology. + * + * (a < 0) | (b >= 0) -> LT|GE = 0b111 but operands differ (param0 vs param1) + * + * bool_info_compatible() rejects the pair on the s1_vr mismatch. + * Negative test: returns 0, OR preserved. */ +UT_TEST(test_setif_or_different_operands_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(0, I32), utb_imm(TOK_LT, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(1, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(1, I32), utb_imm(TOK_GE, I32), UTB_NONE); + int ior = utb_emit(ir, TCCIR_OP_OR, utb_temp(2, I32), + utb_temp(0, I32), utb_temp(1, I32)); + + int changes = tcc_ir_opt_setif_or_tautology(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, ior), TCCIR_OP_OR); + + utb_free(ir); + return 0; +} + +/* Missing-CMP guard: a SETIF whose immediately-preceding non-NOP instruction + * is NOT a CMP yields no recorded boolean, so the OR has nothing to combine. + * + * i0: ASSIGN T0 = #5 (filler so T0 exists; not a CMP) + * i1: SETIF T1, #TOK_LT (preceding non-NOP is ASSIGN, not CMP -> drop) + * i2: CMP a, #0 + * i3: SETIF T2, #TOK_GE (properly tracked) + * i4: OR T3 = T1 | T2 (T1 not tracked -> incompatible -> no fold) + * + * Even though the cond tokens would union to 0b111, the un-tracked SETIF + * source blocks the fold. Negative test: returns 0, OR preserved. */ +UT_TEST(test_setif_or_setif_without_cmp_no_fold) +{ + TCCIRState *ir = utb_new(); + + utb_emit(ir, TCCIR_OP_ASSIGN, utb_temp(0, I32), utb_imm(5, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(1, I32), utb_imm(TOK_LT, I32), UTB_NONE); + utb_emit(ir, TCCIR_OP_CMP, UTB_NONE, utb_param(0, I32), utb_imm(0, I32)); + utb_emit(ir, TCCIR_OP_SETIF, utb_temp(2, I32), utb_imm(TOK_GE, I32), UTB_NONE); + int ior = utb_emit(ir, TCCIR_OP_OR, utb_temp(3, I32), + utb_temp(1, I32), utb_temp(2, I32)); + + int changes = tcc_ir_opt_setif_or_tautology(ir); + + UT_ASSERT_EQ(changes, 0); + UT_ASSERT_EQ(utb_op(ir, ior), TCCIR_OP_OR); + + utb_free(ir); + return 0; +} + +/* ------------------------------------------------------------------ suite */ + +UT_SUITE(opt_setif_or_taut) +{ + UT_COVERS("setif_or_tautology"); + UT_RUN(test_setif_or_lt_ge_covers_all_folds_to_one); + UT_RUN(test_setif_or_eq_ne_covers_all_folds_to_one); + UT_RUN(test_setif_or_lt_eq_partial_no_fold); + UT_RUN(test_setif_or_different_operands_no_fold); + UT_RUN(test_setif_or_setif_without_cmp_no_fold); +} diff --git a/tests/unit/ut.h b/tests/unit/ut.h index 20328a73..88231eb0 100644 --- a/tests/unit/ut.h +++ b/tests/unit/ut.h @@ -70,6 +70,12 @@ extern const char *ut_current_test; fprintf(stderr, " %s %s\n", _ut_failed ? "FAIL" : "ok ", #name); \ } while (0) +/* Annotation: declares that the enclosing suite covers optimization pass + * (a string literal, e.g. UT_COVERS("neg_chain_cse")). Consumed by + * tests/unit/check_pass_coverage.py to build the pass-coverage ledger. Expands + * to a no-op statement so it can sit inside a UT_SUITE body. */ +#define UT_COVERS(pass_name) ((void)sizeof(pass_name)) + #define UT_SUITE(name) void ut_suite_##name(void) #define UT_DECLARE_SUITE(name) void ut_suite_##name(void) #define UT_RUN_SUITE(name) \ From 44e3eade1ce668ef54f89424a2ad68d51d97750c Mon Sep 17 00:00:00 2001 From: Mateusz Stadnik Date: Fri, 26 Jun 2026 23:41:51 +0200 Subject: [PATCH 07/22] adding new tests --- .github/workflows/ci.yml | 5 +- .gitignore | 8 + Makefile | 19 +- docs/plan_optimizer_test_coverage.md | 24 +- docs/plan_whole_tinycc_coverage.md | 307 ++++ ir/codegen.c | 13 + ir/core.c | 29 + ir/dump.c | 43 + ir/opt/ssa_opt.c | 86 +- ir/opt/ssa_opt_dce.c | 4 + ir/opt/ssa_opt_fold.c | 10 + ir/opt/ssa_opt_reassoc.c | 20 + ir/opt_constfold.c | 13 +- ir/opt_constprop.c | 93 +- ir/opt_copyprop.c | 11 +- ir/opt_dead_lea_store.c | 63 + ir/opt_fusion.c | 3 +- ir/opt_knownbits.c | 25 +- ir/opt_loop.c | 11 + ir/opt_loop_utils.c | 21 +- ir/opt_memory.c | 7 +- ir/opt_neg_chain.c | 54 +- ir/opt_utils.c | 39 + ir/opt_utils.h | 6 + ir/regalloc.c | 49 +- scripts/asan_sweep.py | 341 ++++ scripts/asan_sweep.sh | 175 ++ scripts/diff_olevels.py | 167 ++ scripts/diff_vs_gcc.py | 254 +++ scripts/reduce_divergence.py | 131 ++ tccgen.c | 116 +- tccir.h | 14 + tests/Makefile | 2 + tests/frontend/Makefile | 28 + tests/frontend/conftest.py | 57 + tests/frontend/diagnostics/01_undeclared.c | 1 + .../frontend/diagnostics/01_undeclared.stderr | 2 + tests/frontend/diagnostics/02_redefinition.c | 2 + .../diagnostics/02_redefinition.stderr | 2 + tests/frontend/diagnostics/02_type_mismatch.c | 1 + .../diagnostics/02_type_mismatch.stderr | 2 + .../diagnostics/03_incompatible_types.c | 3 + .../diagnostics/03_incompatible_types.stderr | 2 + tests/frontend/diagnostics/03_redefinition.c | 5 + .../diagnostics/03_redefinition.stderr | 2 + .../frontend/diagnostics/04_invalid_lvalue.c | 1 + .../diagnostics/04_invalid_lvalue.stderr | 2 + .../diagnostics/05_incompatible_call.c | 2 + .../diagnostics/05_incompatible_call.stderr | 2 + .../frontend/diagnostics/break_outside_loop.c | 4 + .../diagnostics/break_outside_loop.stderr | 2 + .../diagnostics/continue_outside_loop.c | 4 + .../diagnostics/continue_outside_loop.stderr | 2 + tests/frontend/diagnostics/duplicate_label.c | 6 + .../diagnostics/duplicate_label.stderr | 2 + tests/frontend/diagnostics/invalid_lvalue.c | 5 + .../diagnostics/invalid_lvalue.stderr | 2 + .../diagnostics/missing_closing_brace.c | 1 + .../diagnostics/missing_closing_brace.stderr | 2 + .../frontend/diagnostics/missing_semicolon.c | 1 + .../diagnostics/missing_semicolon.stderr | 2 + tests/frontend/diagnostics/type_mismatch.c | 5 + .../frontend/diagnostics/type_mismatch.stderr | 2 + .../diagnostics/undeclared_identifier.c | 3 + .../diagnostics/undeclared_identifier.stderr | 2 + tests/frontend/diagnostics/void_variable.c | 1 + .../frontend/diagnostics/void_variable.stderr | 2 + tests/frontend/pp/01_macro_expand.c | 2 + tests/frontend/pp/01_macro_expand.expect | 1 + tests/frontend/pp/01_simple_macro.c | 2 + tests/frontend/pp/01_simple_macro.expect | 1 + tests/frontend/pp/02_stringify.c | 2 + tests/frontend/pp/02_stringify.expect | 1 + tests/frontend/pp/03_token_paste.c | 2 + tests/frontend/pp/03_token_paste.expect | 1 + tests/frontend/pp/04_if_expr.c | 5 + tests/frontend/pp/04_if_expr.expect | 1 + tests/frontend/pp/04_variadic.c | 2 + tests/frontend/pp/04_variadic.expect | 1 + tests/frontend/pp/05_ifdef.c | 6 + tests/frontend/pp/05_ifdef.expect | 1 + tests/frontend/pp/empty_macro.c | 2 + tests/frontend/pp/empty_macro.expect | 1 + tests/frontend/pp/include_guard.c | 4 + tests/frontend/pp/include_guard.expect | 1 + tests/frontend/pp/line_continuation.c | 3 + tests/frontend/pp/line_continuation.expect | 1 + tests/frontend/pp/macro_indirection.c | 3 + tests/frontend/pp/macro_indirection.expect | 1 + tests/frontend/pp/macro_undef.c | 4 + tests/frontend/pp/macro_undef.expect | 2 + tests/frontend/pp/pragma_once.c | 2 + tests/frontend/pp/pragma_once.expect | 1 + tests/frontend/pp/predefined_macros.c | 3 + tests/frontend/pp/predefined_macros.expect | 3 + tests/frontend/test_frontend.py | 276 +++ tests/frontend/types/01_int_promotion.c | 1 + tests/frontend/types/01_int_promotion.expect | 15 + tests/frontend/types/02_const_qualifier.c | 5 + .../frontend/types/02_const_qualifier.expect | 9 + tests/frontend/types/02_unsigned_conversion.c | 3 + .../types/02_unsigned_conversion.expect | 12 + tests/frontend/types/03_const_qualifier.c | 3 + .../frontend/types/03_const_qualifier.expect | 15 + tests/frontend/types/04_volatile_qualifier.c | 3 + .../types/04_volatile_qualifier.expect | 15 + tests/frontend/types/05_alignas.c | 5 + tests/frontend/types/05_alignas.expect | 12 + tests/frontend/types/06_bitfield.c | 8 + tests/frontend/types/06_bitfield.expect | 30 + tests/frontend/types/07_vla.c | 5 + tests/frontend/types/07_vla.expect | 41 + tests/frontend/types/08_function_prototype.c | 5 + .../types/08_function_prototype.expect | 18 + tests/frontend/types/09_variadic.c | 5 + tests/frontend/types/09_variadic.expect | 21 + tests/frontend/types/10_noreturn.c | 7 + tests/frontend/types/10_noreturn.expect | 21 + tests/frontend/types/11_static_storage.c | 5 + tests/frontend/types/11_static_storage.expect | 12 + tests/frontend/types/12_extern_storage.c | 5 + tests/frontend/types/12_extern_storage.expect | 12 + tests/frontend/types/13_typedef.c | 5 + tests/frontend/types/13_typedef.expect | 12 + tests/frontend/types/14_enum.c | 5 + tests/frontend/types/14_enum.expect | 12 + tests/frontend/types/15_struct_basic.c | 8 + tests/frontend/types/15_struct_basic.expect | 21 + tests/frontend/types/16_union_basic.c | 8 + tests/frontend/types/16_union_basic.expect | 15 + tests/frontend/types/17_array_decay.c | 3 + tests/frontend/types/17_array_decay.expect | 18 + tests/frontend/types/18_type_cast.c | 3 + tests/frontend/types/18_type_cast.expect | 15 + tests/frontend/types/19_sizeof.c | 4 + tests/frontend/types/19_sizeof.expect | 9 + tests/frontend/types/20_bool.c | 3 + tests/frontend/types/20_bool.expect | 15 + tests/frontend/types/21_constant_init.c | 4 + tests/frontend/types/21_constant_init.expect | 15 + tests/frontend/types/22_designated_init.c | 9 + .../frontend/types/22_designated_init.expect | 33 + tests/frontend/types/23_compound_literal.c | 9 + .../frontend/types/23_compound_literal.expect | 45 + tests/frontend/types/24_pointer_arith.c | 3 + tests/frontend/types/24_pointer_arith.expect | 18 + tests/frontend/types/25_function_pointer.c | 7 + .../frontend/types/25_function_pointer.expect | 30 + tests/frontend/types/26_restrict.c | 3 + tests/frontend/types/26_restrict.expect | 18 + tests/frontend/types/27_long_long.c | 3 + tests/frontend/types/27_long_long.expect | 12 + tests/frontend/types/28_float_type.c | 3 + tests/frontend/types/28_float_type.expect | 18 + tests/frontend/types/29_double_type.c | 3 + tests/frontend/types/29_double_type.expect | 18 + tests/frontend/types/30_inline.c | 7 + tests/frontend/types/30_inline.expect | 30 + tests/fuzz/fuzz_harness.py | 301 ++++ tests/fuzz/gen_c.py | 540 ++++++ tests/fuzz/test_random_c_olevels.py | 94 + tests/fuzz/test_random_c_vs_gcc.py | 117 ++ tests/gcctestsuite/download_gcc_tests.sh | 16 +- tests/ir_tests/asm/cbz_fusion.c | 20 + tests/ir_tests/asm/forward_branch_narrow.c | 18 + tests/ir_tests/asm/r9_spill.c | 11 + tests/ir_tests/asm/struct_packed_9byte.c | 23 + tests/ir_tests/asm/wide_string_merge.c | 6 + tests/ir_tests/conftest.py | 16 + .../golden/block_copy_init/clear_struct.c | 6 + .../block_copy_init/clear_struct.expected | 10 + .../ir_tests/golden/ssa:branch/branch_fold.c | 5 + .../golden/ssa:branch/branch_fold.expected | 7 + tests/ir_tests/golden/ssa:cprop/copy_chain.c | 6 + .../golden/ssa:cprop/copy_chain.expected | 5 + tests/ir_tests/golden/ssa:fold/fold_add.c | 3 + .../golden/ssa:fold/fold_add.expected | 2 + tests/ir_tests/golden/ssa:gvn/common_expr.c | 5 + .../golden/ssa:gvn/common_expr.expected | 4 + .../golden/ssa:load_cse/repeated_load.c | 5 + .../ssa:load_cse/repeated_load.expected | 6 + tests/ir_tests/golden/ssa:narrow/narrow_add.c | 3 + .../golden/ssa:narrow/narrow_add.expected | 4 + tests/ir_tests/golden/ssa:sccp/sccp_loop.c | 9 + .../golden/ssa:sccp/sccp_loop.expected | 9 + tests/ir_tests/test_codegen_asm.py | 225 +++ tests/ir_tests/test_golden_ir.py | 216 +++ tests/run_tests.py | 15 +- tests/unit/Makefile | 11 +- tests/unit/PASS_COVERAGE.md | 475 +++++- tests/unit/README.md | 39 + tests/unit/SOURCE_COVERAGE.md | 145 ++ tests/unit/arm/armv8m/Makefile | 66 +- tests/unit/arm/armv8m/ir_build.h | 143 ++ tests/unit/arm/armv8m/ir_eval.h | 494 ++++++ tests/unit/arm/armv8m/ir_gen.h | 358 ++++ tests/unit/arm/armv8m/stubs.c | 28 +- tests/unit/arm/armv8m/test_ir_dump.c | 109 ++ tests/unit/arm/armv8m/test_ir_operand.c | 251 +++ tests/unit/arm/armv8m/test_ir_stack.c | 132 ++ tests/unit/arm/armv8m/test_main.c | 16 + tests/unit/arm/armv8m/test_metamorphic.c | 795 +++++++++ tests/unit/arm/armv8m/test_metamorphic_ssa.c | 72 + tests/unit/arm/armv8m/test_opt_bitfield.c | 627 +++++++ tests/unit/arm/armv8m/test_opt_cmp_fuse.c | 460 +++++ tests/unit/arm/armv8m/test_opt_cmpfold.c | 695 +++++++- .../arm/armv8m/test_opt_const_aggregate.c | 566 +++++++ tests/unit/arm/armv8m/test_opt_constfold.c | 1367 ++++++++++++++- tests/unit/arm/armv8m/test_opt_constprop.c | 1507 +++++++++++++++++ tests/unit/arm/armv8m/test_opt_copyprop.c | 1074 +++++++++++- .../unit/arm/armv8m/test_opt_dead_lea_store.c | 303 ++++ tests/unit/arm/armv8m/test_opt_dead_vla.c | 555 ++++++ tests/unit/arm/armv8m/test_opt_jump_thread.c | 341 ++++ tests/unit/arm/armv8m/test_opt_knownbits.c | 458 +++++ tests/unit/arm/armv8m/test_opt_licm.c | 401 +++++ tests/unit/arm/armv8m/test_opt_loop_dead.c | 476 ++++++ tests/unit/arm/armv8m/test_opt_neg_chain.c | 310 ++++ tests/unit/arm/armv8m/test_opt_reroll.c | 489 ++++++ .../unit/arm/armv8m/test_opt_setif_or_taut.c | 395 +++++ tests/unit/arm/armv8m/test_opt_xform.c | 590 +++++++ tests/unit/arm/armv8m/test_svalue.c | 91 + tests/unit/gen_source_coverage.py | 277 +++ tests/unit/ut.h | 75 +- 223 files changed, 19027 insertions(+), 268 deletions(-) create mode 100644 docs/plan_whole_tinycc_coverage.md create mode 100755 scripts/asan_sweep.py create mode 100755 scripts/asan_sweep.sh create mode 100644 scripts/diff_olevels.py create mode 100644 scripts/diff_vs_gcc.py create mode 100644 scripts/reduce_divergence.py create mode 100644 tests/frontend/Makefile create mode 100644 tests/frontend/conftest.py create mode 100644 tests/frontend/diagnostics/01_undeclared.c create mode 100644 tests/frontend/diagnostics/01_undeclared.stderr create mode 100644 tests/frontend/diagnostics/02_redefinition.c create mode 100644 tests/frontend/diagnostics/02_redefinition.stderr create mode 100644 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tests/frontend/pp/line_continuation.expect create mode 100644 tests/frontend/pp/macro_indirection.c create mode 100644 tests/frontend/pp/macro_indirection.expect create mode 100644 tests/frontend/pp/macro_undef.c create mode 100644 tests/frontend/pp/macro_undef.expect create mode 100644 tests/frontend/pp/pragma_once.c create mode 100644 tests/frontend/pp/pragma_once.expect create mode 100644 tests/frontend/pp/predefined_macros.c create mode 100644 tests/frontend/pp/predefined_macros.expect create mode 100644 tests/frontend/test_frontend.py create mode 100644 tests/frontend/types/01_int_promotion.c create mode 100644 tests/frontend/types/01_int_promotion.expect create mode 100644 tests/frontend/types/02_const_qualifier.c create mode 100644 tests/frontend/types/02_const_qualifier.expect create mode 100644 tests/frontend/types/02_unsigned_conversion.c create mode 100644 tests/frontend/types/02_unsigned_conversion.expect create mode 100644 tests/frontend/types/03_const_qualifier.c create mode 100644 tests/frontend/types/03_const_qualifier.expect create mode 100644 tests/frontend/types/04_volatile_qualifier.c create mode 100644 tests/frontend/types/04_volatile_qualifier.expect create mode 100644 tests/frontend/types/05_alignas.c create mode 100644 tests/frontend/types/05_alignas.expect create mode 100644 tests/frontend/types/06_bitfield.c create mode 100644 tests/frontend/types/06_bitfield.expect create mode 100644 tests/frontend/types/07_vla.c create mode 100644 tests/frontend/types/07_vla.expect create mode 100644 tests/frontend/types/08_function_prototype.c create mode 100644 tests/frontend/types/08_function_prototype.expect create mode 100644 tests/frontend/types/09_variadic.c create mode 100644 tests/frontend/types/09_variadic.expect create mode 100644 tests/frontend/types/10_noreturn.c create mode 100644 tests/frontend/types/10_noreturn.expect create mode 100644 tests/frontend/types/11_static_storage.c create mode 100644 tests/frontend/types/11_static_storage.expect create mode 100644 tests/frontend/types/12_extern_storage.c create mode 100644 tests/frontend/types/12_extern_storage.expect create mode 100644 tests/frontend/types/13_typedef.c create mode 100644 tests/frontend/types/13_typedef.expect create mode 100644 tests/frontend/types/14_enum.c create mode 100644 tests/frontend/types/14_enum.expect create mode 100644 tests/frontend/types/15_struct_basic.c create mode 100644 tests/frontend/types/15_struct_basic.expect create mode 100644 tests/frontend/types/16_union_basic.c create mode 100644 tests/frontend/types/16_union_basic.expect create mode 100644 tests/frontend/types/17_array_decay.c create mode 100644 tests/frontend/types/17_array_decay.expect create mode 100644 tests/frontend/types/18_type_cast.c create mode 100644 tests/frontend/types/18_type_cast.expect create mode 100644 tests/frontend/types/19_sizeof.c create mode 100644 tests/frontend/types/19_sizeof.expect create mode 100644 tests/frontend/types/20_bool.c create mode 100644 tests/frontend/types/20_bool.expect create mode 100644 tests/frontend/types/21_constant_init.c create mode 100644 tests/frontend/types/21_constant_init.expect create mode 100644 tests/frontend/types/22_designated_init.c create mode 100644 tests/frontend/types/22_designated_init.expect create mode 100644 tests/frontend/types/23_compound_literal.c create mode 100644 tests/frontend/types/23_compound_literal.expect create mode 100644 tests/frontend/types/24_pointer_arith.c create mode 100644 tests/frontend/types/24_pointer_arith.expect create mode 100644 tests/frontend/types/25_function_pointer.c create mode 100644 tests/frontend/types/25_function_pointer.expect create mode 100644 tests/frontend/types/26_restrict.c create mode 100644 tests/frontend/types/26_restrict.expect create mode 100644 tests/frontend/types/27_long_long.c create mode 100644 tests/frontend/types/27_long_long.expect create mode 100644 tests/frontend/types/28_float_type.c create mode 100644 tests/frontend/types/28_float_type.expect create mode 100644 tests/frontend/types/29_double_type.c create mode 100644 tests/frontend/types/29_double_type.expect create mode 100644 tests/frontend/types/30_inline.c create mode 100644 tests/frontend/types/30_inline.expect create mode 100644 tests/fuzz/fuzz_harness.py create mode 100644 tests/fuzz/gen_c.py create mode 100644 tests/fuzz/test_random_c_olevels.py create mode 100644 tests/fuzz/test_random_c_vs_gcc.py create mode 100644 tests/ir_tests/asm/cbz_fusion.c create mode 100644 tests/ir_tests/asm/forward_branch_narrow.c create mode 100644 tests/ir_tests/asm/r9_spill.c create mode 100644 tests/ir_tests/asm/struct_packed_9byte.c create mode 100644 tests/ir_tests/asm/wide_string_merge.c create mode 100644 tests/ir_tests/golden/block_copy_init/clear_struct.c create mode 100644 tests/ir_tests/golden/block_copy_init/clear_struct.expected create mode 100644 tests/ir_tests/golden/ssa:branch/branch_fold.c create mode 100644 tests/ir_tests/golden/ssa:branch/branch_fold.expected create mode 100644 tests/ir_tests/golden/ssa:cprop/copy_chain.c create mode 100644 tests/ir_tests/golden/ssa:cprop/copy_chain.expected create mode 100644 tests/ir_tests/golden/ssa:fold/fold_add.c create mode 100644 tests/ir_tests/golden/ssa:fold/fold_add.expected create mode 100644 tests/ir_tests/golden/ssa:gvn/common_expr.c create mode 100644 tests/ir_tests/golden/ssa:gvn/common_expr.expected create mode 100644 tests/ir_tests/golden/ssa:load_cse/repeated_load.c create mode 100644 tests/ir_tests/golden/ssa:load_cse/repeated_load.expected create mode 100644 tests/ir_tests/golden/ssa:narrow/narrow_add.c create mode 100644 tests/ir_tests/golden/ssa:narrow/narrow_add.expected create mode 100644 tests/ir_tests/golden/ssa:sccp/sccp_loop.c create mode 100644 tests/ir_tests/golden/ssa:sccp/sccp_loop.expected create mode 100644 tests/ir_tests/test_codegen_asm.py create mode 100644 tests/ir_tests/test_golden_ir.py create mode 100644 tests/unit/SOURCE_COVERAGE.md create mode 100644 tests/unit/arm/armv8m/ir_eval.h create mode 100644 tests/unit/arm/armv8m/ir_gen.h create mode 100644 tests/unit/arm/armv8m/test_ir_dump.c create mode 100644 tests/unit/arm/armv8m/test_ir_operand.c create mode 100644 tests/unit/arm/armv8m/test_ir_stack.c create mode 100644 tests/unit/arm/armv8m/test_metamorphic.c create mode 100644 tests/unit/arm/armv8m/test_metamorphic_ssa.c create mode 100644 tests/unit/arm/armv8m/test_opt_bitfield.c create mode 100644 tests/unit/arm/armv8m/test_opt_const_aggregate.c create mode 100644 tests/unit/arm/armv8m/test_opt_dead_vla.c create mode 100644 tests/unit/arm/armv8m/test_opt_loop_dead.c create mode 100644 tests/unit/arm/armv8m/test_opt_reroll.c create mode 100644 tests/unit/arm/armv8m/test_opt_xform.c create mode 100644 tests/unit/arm/armv8m/test_svalue.c create mode 100644 tests/unit/gen_source_coverage.py diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index bd241e2d..857fc2d2 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -25,7 +25,10 @@ jobs: submodules: recursive - name: Configure - run: ./configure --enable-cross --enable-O2 + run: ./configure --enable-cross --enable-O2 + + - name: Source coverage ledger is complete + run: python3 tests/unit/gen_source_coverage.py --check - name: Build and test shell: bash diff --git a/.gitignore b/.gitignore index 6f465adc..06ff2048 100644 --- a/.gitignore +++ b/.gitignore @@ -97,8 +97,16 @@ tests/ir_tests/dump_ir.txt tests/ir_tests/dump.txt tests/ir_tests/dump_fine.txt tests/ir_tests/dump_ir_fine.txt +tests/ir_tests/build/ +armv8m-tcc.debug .aider* .claude .cache scripts/.disasm_cache.json scripts/.disasm_cache.pending.json + +# Python test artifacts +__pycache__/ +.pytest_cache/ +*.pyc +tests/fuzz/results/* \ No newline at end of file diff --git a/Makefile b/Makefile index 9ce4a6dd..6ba9ece1 100644 --- a/Makefile +++ b/Makefile @@ -663,8 +663,18 @@ warn-check: armv8m-tcc$(EXESUF) patch-newlib if [ "$$fail" -ne 0 ]; then exit 1; fi @echo "------------ warn-check: passed ------------" +# run frontend coverage tests +# Fast, QEMU-free preprocessor / type-system / diagnostic golden tests. +test-frontend: cross + @echo "------------ frontend tests ------------" + @if [ "$(USE_VENV)" = "1" ]; then \ + cd $(TOP)/tests/frontend && "$(VENV_PY)" -m pytest -q; \ + else \ + cd $(TOP)/tests/frontend && $(PYTEST) -q; \ + fi + # run IR tests via pytest (preferred) -test: cross test-aeabi-host test-asm warn-check test-venv test-prepare download-gcc-tests ut +test: cross test-aeabi-host test-asm warn-check test-venv test-prepare download-gcc-tests ut test-frontend @echo "------------ ir_tests (pytest) ------------" @if [ "$(USE_VENV)" = "1" ]; then \ cd $(IRTESTS_DIR) && "$(VENV_PY)" -m pytest -s -n $(J) --durations=10; \ @@ -776,10 +786,15 @@ test-valgrind: ut: $(MAKE) -C tests/unit run +# gcov line/branch coverage report for the unit tests (requires gcovr). +# Renders HTML + text under tests/unit//build/coverage/. +ut-coverage: + $(MAKE) -C tests/unit coverage + ut-clean: $(MAKE) -C tests/unit clean -.PHONY: all cross fp-libs clean test test-valgrind test-aeabi-host test-legacy test-tests2 test-gcc-torture test-gcc-torture-compile test-gcc-torture-execute test-full test-all rebuild-newlib download-gcc-tests tar tags ETAGS doc distclean install uninstall ut ut-clean FORCE +.PHONY: all cross fp-libs clean test test-valgrind test-aeabi-host test-legacy test-tests2 test-gcc-torture test-gcc-torture-compile test-gcc-torture-execute test-full test-all rebuild-newlib download-gcc-tests tar tags ETAGS doc distclean install uninstall ut ut-coverage ut-clean FORCE # Container image settings (auto-detect docker or podman) DOCKER_REGISTRY ?= ghcr.io diff --git a/docs/plan_optimizer_test_coverage.md b/docs/plan_optimizer_test_coverage.md index 74c15ab9..7fa81534 100644 --- a/docs/plan_optimizer_test_coverage.md +++ b/docs/plan_optimizer_test_coverage.md @@ -130,6 +130,22 @@ miscompile as a regression test, then broadening; register each in `test_main.c` is subsumed in SSA, diff old-path vs new-path `-dump-ir` for behavioral equivalence. Turns the risky merge into a green/red signal. +### Phase G — Source-tree coverage ledger + generator +Phases A–F focus on optimizer passes and codegen size levers, but most of the tinycc source tree +(frontend, IR core, backend drivers, runtime libs) is only exercised indirectly by end-to-end +QEMU/smoke tests. This phase adds a **file-level coverage ledger** so every TU knows which test +layer covers it and which files have no dedicated coverage. +- **`tests/unit/gen_source_coverage.py`** (new): scans tinycc source files, auto-maps unit suites to + their target TUs, reads `source_coverage_map.json`, and regenerates `SOURCE_COVERAGE.md`. +- **`tests/unit/source_coverage_map.json`** (new): editable ledger mapping each source file to a + coverage kind (`unit`, `golden_ir`, `codegen_asm`, `ir_test`, `smoke`, `runtime_lib`, `tool`, + `partial`, `none`) and the covering test artifact(s). +- **`tests/unit/SOURCE_COVERAGE.md`** (new/generated): human-readable report with summary stats and + per-layer tables. +- **Goal:** every non-runtime source file is either covered by a unit/golden/asm test or explicitly + annotated as `ir_test`/`smoke`/`partial`/`none`; `gen_source_coverage.py --check` fails the CI job + when a new TU is missing from the map or when `SOURCE_COVERAGE.md` is stale. + ## Risk-prioritized first batch Order = (historical-miscompile evidence) × (Phase-4 merge centrality) × (ease of isolated test): 1. `opt_knownbits` 2. `opt_constfold` 3. `opt_constprop` 4. `opt_copyprop` 5. cmp-fold family @@ -149,8 +165,10 @@ Order = (historical-miscompile evidence) × (Phase-4 merge centrality) × (ease - `make ut` — all unit suites pass, `0 failed`; each Tier-1 suite **fails first** if its target fix is reverted (proves it bites). - `make test-opt` — golden-IR + codegen pytest modules pass; `--update` regenerates goldens. -- `python tests/unit/check_pass_coverage.py` — prints the gap list; after Phase F exits non-zero +- `python tests/unit/check_pass_coverage.py` — prints the pass gap list; after Phase F exits non-zero on any uncovered registered pass. +- `python tests/unit/gen_source_coverage.py` — regenerates `SOURCE_COVERAGE.md`; after Phase G exits + non-zero on any tracked source file missing from `source_coverage_map.json`. - Determinism spot-check: run a golden case twice, confirm byte-identical `=== AFTER ===`. - No regression of the existing slow path: full `tests/smoke/tcc_suite_test.py` / `tests/ir_tests/test_qemu.py` still pass. @@ -159,7 +177,9 @@ Order = (historical-miscompile evidence) × (Phase-4 merge centrality) × (ease - **New:** `tests/unit/arm/armv8m/ir_build.{h,c}`, `tests/unit/arm/armv8m/test_opt_{knownbits,constfold,constprop,copyprop,cmpfold,licm}.c`; `tests/ir_tests/test_golden_ir.py`, `tests/ir_tests/golden/`; `tests/ir_tests/test_codegen_asm.py`; - `tests/unit/check_pass_coverage.py`, `tests/unit/PASS_COVERAGE.md`. + `tests/unit/check_pass_coverage.py`, `tests/unit/PASS_COVERAGE.md`; + `tests/unit/gen_source_coverage.py`, `tests/unit/source_coverage_map.json`, + `tests/unit/SOURCE_COVERAGE.md`. - **Modify:** `tests/unit/ut.h`, `tests/unit/arm/armv8m/Makefile`, `tests/unit/arm/armv8m/test_main.c`, `tests/unit/arm/armv8m/{stubs.c,tcc_state_stub.c}` (as link gaps surface), `Makefile`. - **Reuse (read, don't reinvent):** `tccir_operand.h` (`irop_make_*`), `tccir.h` diff --git a/docs/plan_whole_tinycc_coverage.md b/docs/plan_whole_tinycc_coverage.md new file mode 100644 index 00000000..9d47ab49 --- /dev/null +++ b/docs/plan_whole_tinycc_coverage.md @@ -0,0 +1,307 @@ +# Plan: Whole tinycc implementation coverage + +> Extends `docs/plan_optimizer_test_coverage.md` (optimizer + codegen size levers) +> to a **source-tree-wide coverage strategy** for the entire ARMv8-M TinyCC fork. +> Goal: every subsystem — frontend, IR, backend, linker, runtime, self-host — has +> a defined, machine-checkable test layer and a CI gate that catches regressions +> per-commit instead of per-device-boot. + +## Context + +The optimizer plan (`docs/plan_optimizer_test_coverage.md`) is now mostly landed: +`PASS_COVERAGE.md` tracks registered passes, `SOURCE_COVERAGE.md` tracks 118 source +files, unit suites cover 42 files, and golden-IR/codegen-asm harnesses exist. That +work is **pass-centric**. Most of the rest of the compiler (preprocessor, parser, +type system, IR construction, backend instruction selection, register allocation, +ELF/linker, debug info, runtime libraries, the libtcc API, and the self-host +bootstrap) is still only exercised indirectly by the QEMU `ir_tests` corpus and +smoke tests. + +This plan names the missing layers, reuses the existing harnesses where possible, +and adds new ones where the subsystem's contract is not naturally tested by the +optimizer work. + +## Subsystem map and current state + +| Subsystem | Key files | Current coverage | Gap | +|---|---|---|---| +| **Preprocessor** | `tccpp.c` | QEMU `ir_tests` corpus only | No isolated lexer/macro/tests2 test | +| **Parser + semantic** | `tccgen.c`, `svalue.c`, `tccir_operand.c` | QEMU corpus + unit base link | No per-feature unit tests | +| **IR core** | `ir/core.c`, `ir/vreg.c`, `ir/pool.c`, `ir/type.c`, `ir/dump.c`, `ir/stack.c` | `ir_pool/type/vreg` unit suites; rest via QEMU | `core`, `dump`, `stack` need targeted tests | +| **Optimizer** | `ir/opt*.c`, `ir/licm.c`, `ir/opt/ssa_opt*.c` | 11 legacy unit suites, 7 SSA golden cases, ledger | Many registered passes still uncovered | +| **Register allocation** | `tccls.c`, `ir/live.c`, `ir/regalloc.c`, `arch/arm/arm_regalloc.c`, `arch/arm/ssa_opt_arm.c` | QEMU corpus only | No isolated RA/interval tests | +| **Backend codegen** | `arm-thumb-gen.c`, `ir/codegen.c`, `ir/machine_op.c`, `tccmachine.c` | QEMU corpus + 5 codegen-asm characterizations | No per-IR-op backend unit tests | +| **Thumb encoder** | `arch/arm/thumb/thop_*.c`, `arch/arm/thumb/thumb.c` | 27 `thop_*` unit suites | `thop_alu_imm`, `thop_dsp` not unit-tested | +| **Inline asm** | `tccasm.c`, `arm-thumb-asm.c`, `thumb-tok.h` | QEMU corpus + `tests/thumb/armv8m/*.S` | Assembler parser has no host unit tests | +| **AAPCS / calls** | `arch/arm/arm_aapcs.c`, `arm-thumb-callsite.c`, `arm-link.c` | QEMU corpus only | ABI edge cases not isolated | +| **Object / linker** | `tccelf.c`, `tccld.c`, `tccyaff.c` | QEMU corpus only | No ELF/linker unit tests | +| **Debug info** | `tccdbg.c`, `tccdebug.c` | QEMU corpus only | No DWARF/STAB unit tests | +| **libtcc API** | `libtcc.c` | QEMU corpus + `tests/libtcc_test*.c` | API not run in CI | +| **Runtime libs** | `lib/*.c`, `lib/*.S`, `lib/fp/*` | exercised by compiled programs | No per-helper unit tests | +| **Self-host bootstrap** | cross/native build, `tests/tests2/*` | smoke tests, manual debugging guide | No automated self-host validation | +| **Tools / scripts** | `scripts/*`, `tcctools.c` | ad-hoc | No regression tests for tooling | + +## Strategy: layered coverage + +Reuse the three mechanisms already proven: + +1. **Isolated `ut.h` unit tests** (`tests/unit/arm/armv8m/`) for pure functions, + data structures, and IR-algorithm modules. +2. **Golden-IR snapshots** (`tests/ir_tests/golden/`) for passes whose output is + deterministic and whose input is easier to write in C than in IR. +3. **Codegen disassembly tests** (`tests/ir_tests/asm/`) for backend emission + contracts tied to size/correctness. + +Add three new layers for the rest of the compiler: + +4. **Frontend feature tests** (`tests/frontend//`) — tiny `.c` inputs + that exercise a single parser/type/semantic construct, compiled host-side with + the debug cross and asserted against IR snapshots, diagnostics, or object + symbols. No QEMU. +5. **Object/linker golden tests** (`tests/linker/`) — small TUs and linker + scripts, compiled to object/ELF/YAFF, then inspected with `readelf`/`objdump` + and compared to golden relocations/section layouts. +6. **Self-host smoke gate** — an automated FAT-drive round-trip that rebuilds a + test with the device native `tcc` and asserts the result matches the host cross. + +A single **coverage ledger** (`source_coverage_map.json` / `SOURCE_COVERAGE.md`) +already covers the source tree; this plan extends the *kind* annotations and adds +the new layers to the generator. + +## Phases + +### Phase 0 — Finish the optimizer plan first + +Do not expand into new subsystems until the existing optimizer work is closed: + +- [ ] `check_pass_coverage.py` enumerates `PASS`/`PASS_GATED` names in + `ir/opt_pipeline.c`, diffs against `UT_COVERS(...)` markers + golden dirs, and + flips to a hard CI fail on any uncovered registered pass. +- [ ] All registered passes in `propagation_passes`, `memory_passes`, + `late_cleanup_passes`, `entry_store_passes`, and SSA tables have at least one + test. +- [ ] The legacy↔SSA equivalence harness (Phase F) exists and runs on a small + corpus. + +> This phase is a prerequisite because the optimizer plan already owns most of the +> current active work; expanding scope before it is complete diffuses effort. + +### Phase 1 — Frontend coverage layer ✅ Implemented + +Target: parser/type/semantic features that are hard to unit-test in isolation but +have clear input/output contracts. + +Implemented in `libs/tinycc/tests/frontend/` with a shared pytest harness +(`conftest.py` + `test_frontend.py`). Registered in `make test` via a new +`test-frontend` target and in `run_tests.py --frontend`. + +Run: +```bash +make -C libs/tinycc test-frontend +# or +cd libs/tinycc/tests && python run_tests.py --frontend -q +``` + +#### 1a. Preprocessor/lexer ✅ + +`tests/frontend/pp/` (14 cases): +- macro expansion order, variadic macros, stringification, token pasting. +- `#if`/`#ifdef` integer constant evaluation edges. +- include-path resolution, pragma handling, `#undef`, predefined macros. + +Mechanism: run `armv8m-tcc -E -P` and diff stdout against `.expect`. Builtin +preamble is stripped and `__DATE__`/`__TIME__` are normalized for stable goldens. + +#### 1b. Type system / semantic analysis ✅ + +`tests/frontend/types/` (31 cases): +- arithmetic conversions, qualifiers (`const`, `volatile`, `restrict`), + `_Alignas`, bit-fields, VLA. +- function types, variadics, `_Noreturn`, storage classes, `inline`, `typedef`, + `enum`. +- initializer folding, designated initializers, compound literals. +- `struct` / `union`, array decay, pointer arithmetic, casts, `sizeof`, `_Bool`, + `long long`, `float`, `double`. + +Mechanism: run `armv8m-tcc -dump-ir -c` and diff stdout against `.expect`. +The harness auto-falls back to `armv8m-tcc.debug` when the release cross does +not expose `-dump-ir`. + +#### 1c. Parser diagnostics ✅ + +`tests/frontend/diagnostics/` (16 cases): +- Expected-error tests for undeclared identifier, type mismatch, redefinition, + invalid lvalue, incompatible call, missing semicolon/brace, break/continue + outside loop, duplicate label, void variable. +- Mechanism: compile with `-Werror`, expect non-zero exit, assert every + non-empty line of `.stderr` appears as a substring of the captured stderr. + +### Phase 2 — IR core + data-structure coverage + +Extend the unit harness to modules that are currently only linked as dead-weight +in the optimizer suites: + +- `ir/core.c` — add `test_ir_core.c`: instruction append/insert/delete, operand + packing, `tcc_ir_put` front-end coupling points, nop compaction. +- `ir/dump.c` — add `test_ir_dump.c`: deterministic output, pass-name matching, + ANSI-color gating. This directly protects the golden-IR harness. +- `ir/stack.c` — add `test_ir_stack.c`: stack slot allocation, VLA frame layout. +- `ir/ssa.c` — add `test_ir_ssa.c`: phi insertion, rename tables, dominator frontiers. +- `svalue.c` / `tccir_operand.c` — add `test_svalue.c` and `test_ir_operand.c`: + operand constructors, type tagging, constant folding helpers. + +### Phase 3 — Register allocation coverage + +RA bugs are a major self-host miscompile class. Add unit tests around: + +- `ir/live.c` — interval construction for straight-line, loops, and calls. +- `tccls.c` — linear scan allocation/spill decisions, callee-saved save/restore. +- `ir/regalloc.c` — phi resolution, phi-copy scheduling, split/merge live ranges. +- `arch/arm/arm_regalloc.c` / `arch/arm/ssa_opt_arm.c` — target-specific + constraints, coalescing, hard-float register classes. + +Mechanism: hand-built IR with known live ranges → assert assigned physical +registers or spill slots. Keep tests deterministic by pinning the allocator's +heuristics (e.g., fixed instruction order, no coalescing surprises). + +### Phase 4 — Backend + codegen coverage + +Extend the codegen-asm harness from five size-lever characterizations to +per-instruction-family correctness tests: + +- Arithmetic: `ADD/SUB/MUL/DIV/IMOD` with all operand shapes (imm/reg/variadic). +- Memory: `LOAD/STORE/LEA/LOAD_INDEXED/STORE_INDEXED` with all addressing modes. +- Control: `JUMP/JUMPIF/IJUMP/SWITCH_TABLE` and branch narrowing. +- Calls: parameter marshalling per AAPCS, return-value handling, tail calls. +- Floating point: soft-float vs hard-float lowering, VFP instruction selection. +- Atomics / exclusive ops: map IR ops to LDREX/STREX loops or V8-M atomics. + +Also add backend unit tests for: +- `ir/codegen.c` — dry-run vs real-run dispatch, two-pass loop invariants. +- `ir/machine_op.c` — machine-op creation and lowering. +- `tccmachine.c` — machine-level store/assign helpers. + +### Phase 5 — Object, linker, and debug info coverage + +These are currently the weakest areas. Add host-side golden tests: + +- `tests/linker/relocations/` — compile small C snippets to ELF, assert relocation + types/symbols via `arm-none-eabi-readelf -r`. +- `tests/linker/sections/` — assert section order, alignment, and merging. +- `tests/linker/yaff/` — if YAFF remains supported, assert YAFF output structure. +- `tests/debug/dwarf/` — compile with `-g`, inspect `.debug_info` / `.debug_line` + for key DIEs and line-number programs. +- `tests/debug/stab/` — same for STAB if still in use. + +Target files: +- `tccelf.c`, `tccld.c`, `tccyaff.c`, `tccdbg.c`, `tccdebug.c`. + +### Phase 6 — Runtime library coverage + +The runtime libs (`lib/*.c`, `lib/*.S`, `lib/fp/*`) are exercised by compiled +programs, but helpers are rarely tested in isolation. Add: + +- Host-native unit tests for pure software-FP helpers (`lib/fp/soft/*.c`) where + the algorithm is architecture-independent. +- Cross-compiled mini-tests for `__aeabi_*`, `__muldi3`, `__divsi3`, `memcpy`, + `memset`, `longjmp`, and VLA helpers. +- Coverage for `lib/armv8m_eabi.c`, `lib/armeabi.c`, `lib/builtin.c`. + +### Phase 7 — libtcc API + tooling coverage + +- Run `tests/libtcc_test.c` and `tests/libtcc_test_mt.c` in CI against the built + `libtcc.a`. +- Add a minimal API test for the ARMv8-M cross target: compile a string in memory, + extract the code, and check the first instruction bytes. +- Add regression tests for helper scripts (`scripts/qemu_fatdisk_run.py`, + `scripts/create_disk.py`, etc.) using a tiny synthetic FAT image. + +### Phase 8 — Self-host bootstrap gate + +The self-host miscompile guide (`docs/selfhost_miscompile_debugging.md`) is +manual. Automate the critical path: + +- A nightly or slow CI job that: + 1. Builds the cross and native `tcc`. + 2. Runs a curated subset of `tests/tests2/` through the FAT-drive + round-trip (put source, compile on device, run, compare output to host cross). + 3. Fails on any behavioral divergence. +- A lighter PR gate: compile the tinycc source with the cross and run a small + subset of `tests/tests2/` through the resulting native binary on QEMU without + rebuilding the kernel (reuse a prebuilt kernel + FAT swap of a smaller test + harness if possible). + +### Phase 9 — Coverage ledger + CI gate + +Extend the existing generator: + +- Update `source_coverage_map.json` kinds to include the new layers: + `frontend`, `ra`, `backend_unit`, `linker`, `debug`, `runtime_unit`, + `libtcc_api`, `selfhost`. +- `gen_source_coverage.py --check` fails on any source file missing from the map + or any stale `SOURCE_COVERAGE.md`. +- Add a CI job that runs the new frontend/linker/debug/runtime suites and the + self-host gate. + +## Risk-prioritized first batch + +Order = (self-host miscompile frequency) × (isolation difficulty) × (blast radius +of a bug): + +1. **RA / live intervals** (Phase 3) — matches the current biggest failure class. +2. **IR core / dump** (Phase 2) — cheap, protects every golden-IR test. +3. **Backend per-op codegen** (Phase 4) — high value, can reuse codegen-asm harness. +4. **Frontend type/parser** (Phase 1) — large surface but many tiny tests. +5. **Object/linker** (Phase 5) — needed before any ELF format changes. +6. **Self-host gate** (Phase 8) — the only end-to-end proof for the cross. + +## Verification + +- `make ut` stays green and grows by the new unit suites. +- `pytest tests/frontend/` passes host-side. +- `pytest tests/linker/` passes host-side. +- `pytest tests/ir_tests/test_codegen_asm.py` covers backend correctness, not + just size levers. +- `make test-selfhost` or the nightly job shows zero divergence on the curated + `tests2` subset. +- `python3 tests/unit/gen_source_coverage.py --check` passes in CI. + +## Files / deliverables + +New: +- `docs/plan_whole_tinycc_coverage.md` (this file). +- `tests/frontend/` tree with runner. +- `tests/linker/` tree with runner. +- `tests/debug/` tree with runner. +- `tests/unit/arm/armv8m/test_ir_{core,dump,stack,ssa,operand,svalue}.c`. +- `tests/unit/arm/armv8m/test_ra_{live,linearscan,phi,arm}.c`. +- `tests/unit/arm/armv8m/test_codegen_{arith,mem,control,call,fp,atomic}.c`. +- `tests/unit/arm/armv8m/test_thop_{alu_imm,dsp}.c`. +- `tests/unit/arm/armv8m/test_libtcc_api.c`. +- `tests/fuzz/` for O-level self-consistency and metamorphic fuzzing (already + referenced by `docs/plan_bug_hunting.md`). +- `scripts/test_selfhost_fat.sh` or similar. + +Modify: +- `tests/unit/ut.h` — add `UT_ASSERT_STREQ` when golden/snapshot asserts land. +- `tests/unit/arm/armv8m/Makefile` — new TUs under test. +- `tests/unit/arm/armv8m/test_main.c` — register new suites. +- `tests/unit/source_coverage_map.json` — annotate new files and layers. +- `.github/workflows/ci.yml` — new jobs for frontend, linker, self-host. + +## Relationship to other plans + +- `docs/plan_optimizer_test_coverage.md` — this plan's **Phase 0**. +- `docs/plan_binary_size_reduction.md` — codegen-asm tests from this plan become + the regression lock for size levers. +- `docs/plan_bug_hunting.md` — fuzz/metamorphic tracks feed bugs into the + appropriate subsystem suite. +- `docs/selfhost_miscompile_debugging.md` — the self-host gate (Phase 8) + operationalizes the manual workflow. + +## Stop criterion + +Every non-test source file in `libs/tinycc/` is listed in +`source_coverage_map.json` with a kind other than `ir_test` or `none`, and every +CI job that corresponds to a kind is green. Until then, `gen_source_coverage.py +--check` fails the build. diff --git a/ir/codegen.c b/ir/codegen.c index 21ef60c4..5b2d2d28 100644 --- a/ir/codegen.c +++ b/ir/codegen.c @@ -1808,6 +1808,7 @@ void tcc_ir_codegen_generate(TCCIRState *ir) memset(orig_ir_to_code_mapping, 0xFF, sizeof(uint32_t) * ir->orig_ir_to_code_mapping_size); /* Track addresses of return jumps for later backpatching to epilogue */ int *return_jump_addrs = tcc_malloc(sizeof(int) * ir->next_instruction_index); + ir->codegen_return_jump_addrs = return_jump_addrs; int num_return_jumps = 0; /* --- DEBUG: catch codegen-time corruption of a spilled temp's allocation.r0. @@ -2108,6 +2109,8 @@ void tcc_ir_codegen_generate(TCCIRState *ir) * Both arrays are declared before #if so they are visible in both passes. */ int *dry_insn_scratch = tcc_mallocz(ir->next_instruction_index * sizeof(int)); uint16_t *dry_insn_saves = tcc_mallocz(ir->next_instruction_index * sizeof(uint16_t)); + ir->codegen_dry_insn_scratch = dry_insn_scratch; + ir->codegen_dry_insn_saves = dry_insn_saves; /* ============================================================================ * OPTION A: Skip dry-run for scratch-conflict-free functions @@ -2286,6 +2289,7 @@ void tcc_ir_codegen_generate(TCCIRState *ir) MopArgs *mop_cache = (!can_skip_dry_run && ir->next_instruction_index > 0) ? tcc_malloc(ir->next_instruction_index * sizeof(MopArgs)) : NULL; + ir->codegen_mop_cache = mop_cache; int use_mop_cache = 0; const int pass_start = can_skip_dry_run ? 1 : 0; @@ -2306,6 +2310,7 @@ void tcc_ir_codegen_generate(TCCIRState *ir) if (ir->next_instruction_index > 0) { branch_target_reset = tcc_mallocz((size_t)ir->next_instruction_index); + ir->codegen_branch_target_reset = branch_target_reset; int has_indirect_jump = 0; for (int bi = 0; bi < ir->next_instruction_index; bi++) { @@ -4218,6 +4223,7 @@ void tcc_ir_codegen_generate(TCCIRState *ir) if (cbz_dry_mapping) tcc_free(cbz_dry_mapping); cbz_dry_mapping = tcc_malloc(ir->ir_to_code_mapping_size * sizeof(uint32_t)); + ir->codegen_cbz_dry_mapping = cbz_dry_mapping; memcpy(cbz_dry_mapping, ir_to_code_mapping, ir->ir_to_code_mapping_size * sizeof(uint32_t)); /* Check if LR was pushed during dry run in a leaf function */ @@ -4303,6 +4309,7 @@ void tcc_ir_codegen_generate(TCCIRState *ir) /* Interval table was mutated: cached MopArgs are stale, discard. */ tcc_free(mop_cache); mop_cache = NULL; + ir->codegen_mop_cache = NULL; } use_mop_cache = (mop_cache != NULL); } @@ -4381,10 +4388,13 @@ void tcc_ir_codegen_generate(TCCIRState *ir) } tcc_free(mop_cache); + ir->codegen_mop_cache = NULL; if (cbz_dry_mapping) tcc_free(cbz_dry_mapping); + ir->codegen_cbz_dry_mapping = NULL; if (branch_target_reset) tcc_free(branch_target_reset); + ir->codegen_branch_target_reset = NULL; ir_to_code_mapping[ir->next_instruction_index] = ind; orig_ir_to_code_mapping[ir->orig_ir_to_code_mapping_size - 1] = ind; @@ -4420,8 +4430,11 @@ void tcc_ir_codegen_generate(TCCIRState *ir) } tcc_free(return_jump_addrs); + ir->codegen_return_jump_addrs = NULL; tcc_free(dry_insn_saves); + ir->codegen_dry_insn_saves = NULL; tcc_free(dry_insn_scratch); + ir->codegen_dry_insn_scratch = NULL; } /* ============================================================================ diff --git a/ir/core.c b/ir/core.c index de082370..23988fcc 100644 --- a/ir/core.c +++ b/ir/core.c @@ -207,6 +207,35 @@ void tcc_ir_free(TCCIRState *ir) tcc_free(ir->parameters_live_intervals); } + if (ir->barrel_shifts) + { + tcc_free(ir->barrel_shifts); + ir->barrel_shifts = NULL; + } + if (ir->shift64_dead_half) + { + tcc_free(ir->shift64_dead_half); + ir->shift64_dead_half = NULL; + } + if (ir->bfi_params) + { + tcc_free(ir->bfi_params); + ir->bfi_params = NULL; + } + + tcc_free(ir->codegen_return_jump_addrs); + ir->codegen_return_jump_addrs = NULL; + tcc_free(ir->codegen_dry_insn_scratch); + ir->codegen_dry_insn_scratch = NULL; + tcc_free(ir->codegen_dry_insn_saves); + ir->codegen_dry_insn_saves = NULL; + tcc_free(ir->codegen_mop_cache); + ir->codegen_mop_cache = NULL; + tcc_free(ir->codegen_cbz_dry_mapping); + ir->codegen_cbz_dry_mapping = NULL; + tcc_free(ir->codegen_branch_target_reset); + ir->codegen_branch_target_reset = NULL; + if (ir->stack_layout.slots != NULL) { tcc_free(ir->stack_layout.slots); diff --git a/ir/dump.c b/ir/dump.c index 862d1137..a80d17a4 100644 --- a/ir/dump.c +++ b/ir/dump.c @@ -622,6 +622,49 @@ void tcc_ir_dump_set_show_physical_regs(int show) show_physical_regs = show; } +/* Returns 1 if `pass_name` is selected by the comma-separated -dump-ir-passes= + * list in s->dump_ir_passes (or the list contains the special token "all"). */ +int tcc_ir_dump_passes_match(TCCState *s, const char *pass_name) +{ + if (!s || !s->dump_ir_passes || !pass_name) + return 0; + const char *p = s->dump_ir_passes; + size_t name_len = strlen(pass_name); + while (*p) + { + const char *comma = strchr(p, ','); + size_t tok_len = comma ? (size_t)(comma - p) : strlen(p); + if (tok_len == 3 && !memcmp(p, "all", 3)) + return 1; + if (tok_len == name_len && !memcmp(p, pass_name, name_len)) + return 1; + if (!comma) + break; + p = comma + 1; + } + return 0; +} + +/* If pass_name is selected by -dump-ir-passes=, print the IR labeled with the + * pass name as "=== AFTER ===" ... "=== END AFTER ===". Shared by + * the legacy optimize loop (tccgen.c RUN_PASS / dump_ir_after_pass) and the SSA + * optimizer driver (ir/opt/ssa_opt.c) so every pass is observable the same way. + * A no-op unless built with CONFIG_TCC_DEBUG. */ +void tcc_ir_dump_after_pass(TCCIRState *ir, const char *pass_name) +{ +#ifdef CONFIG_TCC_DEBUG + if (!tcc_ir_dump_passes_match(tcc_state, pass_name)) + return; + tcc_ir_dump_set_show_physical_regs(0); + printf("=== AFTER %s ===\n", pass_name); + tcc_ir_show(ir); + printf("=== END AFTER %s ===\n", pass_name); +#else + (void)ir; + (void)pass_name; +#endif +} + /* Get the short prefix for a vreg type: V, T, or P */ static char vreg_type_prefix(int vreg) { diff --git a/ir/opt/ssa_opt.c b/ir/opt/ssa_opt.c index 2d35f97a..3d6a70ae 100644 --- a/ir/opt/ssa_opt.c +++ b/ir/opt/ssa_opt.c @@ -357,6 +357,24 @@ static void ssa_opt_rewrite_operand(IRSSAOptCtx *ctx, int instr_idx, } } +static int ssa_opt_use_is_barrel_shift_src2(IRSSAOptCtx *ctx, IRSSAUse use, + int32_t old_vr) +{ + if (use.kind != SSA_USE_INSTR) + return 0; + + TCCIRState *ir = ctx->ir; + IRQuadCompact *q = &ir->compact_instructions[use.idx]; + if (!ir->barrel_shifts || q->orig_index < 0 || + q->orig_index > ir->max_orig_index || + ir->barrel_shifts[q->orig_index] == 0 || + !irop_config[q->op].has_src2) + return 0; + + IROperand src2 = tcc_ir_op_get_src2(ir, q); + return irop_get_vreg(src2) == old_vr; +} + static void ssa_opt_rewrite_phi_operand(IRSSAOptCtx *ctx, int block, int slot, int32_t old_vr, int32_t new_vr) @@ -379,6 +397,16 @@ int ssa_opt_replace_all_uses(IRSSAOptCtx *ctx, int32_t old_vr, int32_t new_vr) if (!old_vi) return 0; + /* ARM barrel-shift fusion encodes a hidden shift on an instruction's src2 + * in ir->barrel_shifts[orig_index]. Replacing that src2 with another vreg + * or an immediate drops the implicit "this operand must be shifted" value + * identity from SSA's point of view. Leave such defs in place so codegen + * still materializes the shift source exactly as fusion recorded it. */ + for (int i = 0; i < old_vi->use_count; i++) { + if (ssa_opt_use_is_barrel_shift_src2(ctx, old_vi->uses[i], old_vr)) + return 0; + } + int count = 0; while (old_vi->use_count > 0) { IRSSAUse use = old_vi->uses[--old_vi->use_count]; @@ -652,45 +680,42 @@ int tcc_ir_ssa_opt_run(IRSSAOptCtx *ctx) const int max_iterations = 5; int changes; + /* Run one SSA pass, accumulate its change count, then make it observable: + * dbg_scan_imm_dest() for the SCAN_IMM_DEST bug hunt and + * tcc_ir_dump_after_pass() for -dump-ir-passes= golden snapshots + * (mirrors the legacy RUN_PASS macro in tccgen.c). */ +#define SSA_RUN(name, call) \ + do \ + { \ + changes += (call); \ + dbg_scan_imm_dest(ctx->ir, name); \ + tcc_ir_dump_after_pass(ctx->ir, name); \ + } while (0) + do { changes = 0; iteration++; /* target-independent passes */ - changes += ssa_opt_var_const_fold(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:var_const_fold"); - changes += ssa_opt_sccp(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:sccp"); - changes += ssa_opt_cprop(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:cprop"); + SSA_RUN("ssa:var_const_fold", ssa_opt_var_const_fold(ctx)); + SSA_RUN("ssa:sccp", ssa_opt_sccp(ctx)); + SSA_RUN("ssa:cprop", ssa_opt_cprop(ctx)); /* Collapse `V <- val [STORE]; ... PARAM V` into `... PARAM val` when V * has a single def and that lone PARAM as its only use. Catches the * inlined-check1 pattern that spills printf args into VARs ahead of * the conditional branch even when only the FAIL path reads them. */ - changes += ssa_opt_var_to_param_forward(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:var_to_param_forward"); - changes += ssa_opt_fold(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:fold"); - changes += ssa_opt_load_cse(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:load_cse"); - changes += ssa_opt_branch(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:branch"); - changes += ssa_opt_cmp_eq_prop(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:cmp_eq_prop"); - changes += ssa_opt_reassoc(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:reassoc"); - changes += ssa_opt_strength(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:strength"); - changes += ssa_opt_narrow(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:narrow"); - changes += ssa_opt_gvn(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:gvn"); - changes += ssa_opt_phi_simplify(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:phi_simplify"); - changes += ssa_opt_dead_loop(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:dead_loop"); - changes += ssa_opt_dce(ctx); - dbg_scan_imm_dest(ctx->ir, "ssa:dce"); + SSA_RUN("ssa:var_to_param_forward", ssa_opt_var_to_param_forward(ctx)); + SSA_RUN("ssa:fold", ssa_opt_fold(ctx)); + SSA_RUN("ssa:load_cse", ssa_opt_load_cse(ctx)); + SSA_RUN("ssa:branch", ssa_opt_branch(ctx)); + SSA_RUN("ssa:cmp_eq_prop", ssa_opt_cmp_eq_prop(ctx)); + SSA_RUN("ssa:reassoc", ssa_opt_reassoc(ctx)); + SSA_RUN("ssa:strength", ssa_opt_strength(ctx)); + SSA_RUN("ssa:narrow", ssa_opt_narrow(ctx)); + SSA_RUN("ssa:gvn", ssa_opt_gvn(ctx)); + SSA_RUN("ssa:phi_simplify", ssa_opt_phi_simplify(ctx)); + SSA_RUN("ssa:dead_loop", ssa_opt_dead_loop(ctx)); + SSA_RUN("ssa:dce", ssa_opt_dce(ctx)); /* target-specific generators (registered by backend) */ if (target_gens && target_gen_count > 0) @@ -698,6 +723,7 @@ int tcc_ir_ssa_opt_run(IRSSAOptCtx *ctx) total += changes; } while (changes > 0 && iteration < max_iterations); +#undef SSA_RUN return total; } diff --git a/ir/opt/ssa_opt_dce.c b/ir/opt/ssa_opt_dce.c index a4d0f42c..4ff6317d 100644 --- a/ir/opt/ssa_opt_dce.c +++ b/ir/opt/ssa_opt_dce.c @@ -729,6 +729,10 @@ static int dce_dead_phi_cycles(IRSSAOptCtx *ctx) vi->use_count--; } *pp = phi->next; + /* Free the unlinked node — it is no longer reachable from block_phis, + * so tcc_ir_ssa_free would otherwise never reclaim it. */ + tcc_free(phi->operands); + tcc_free(phi); changes++; continue; } diff --git a/ir/opt/ssa_opt_fold.c b/ir/opt/ssa_opt_fold.c index 7353e2b8..2a205e21 100644 --- a/ir/opt/ssa_opt_fold.c +++ b/ir/opt/ssa_opt_fold.c @@ -23,6 +23,13 @@ * x - x, x ^ x → 0 * ============================================================================ */ +static int has_barrel_shift_annotation(TCCIRState *ir, const IRQuadCompact *q) +{ + return ir->barrel_shifts && q->orig_index >= 0 && + q->orig_index <= ir->max_orig_index && + ir->barrel_shifts[q->orig_index] != 0; +} + /* Resolve a vreg operand back to its constant defining ASSIGN, if any. * In SSA a TEMP is single-def, so following its def to an ASSIGN #imm gives * the value the operand will carry at runtime. Returns 1 and sets *out_val @@ -69,6 +76,9 @@ static int fold_binary(IRSSAOptCtx *ctx, int idx) IROperand src2 = tcc_ir_op_get_src2(ir, q); IROperand dest = tcc_ir_op_get_dest(ir, q); + if (has_barrel_shift_annotation(ir, q)) + return 0; + int32_t dest_vr = irop_get_vreg(dest); if (dest_vr < 0 || TCCIR_DECODE_VREG_TYPE(dest_vr) != TCCIR_VREG_TYPE_TEMP) return 0; diff --git a/ir/opt/ssa_opt_reassoc.c b/ir/opt/ssa_opt_reassoc.c index 746a7f4e..08a88754 100644 --- a/ir/opt/ssa_opt_reassoc.c +++ b/ir/opt/ssa_opt_reassoc.c @@ -33,6 +33,13 @@ * so we don't increase register pressure. * ============================================================================ */ +static int has_barrel_shift_annotation(TCCIRState *ir, const IRQuadCompact *q) +{ + return ir->barrel_shifts && q->orig_index >= 0 && + q->orig_index <= ir->max_orig_index && + ir->barrel_shifts[q->orig_index] != 0; +} + static int reassoc_binary(IRSSAOptCtx *ctx, int idx) { TCCIRState *ir = ctx->ir; @@ -46,6 +53,13 @@ static int reassoc_binary(IRSSAOptCtx *ctx, int idx) if (src2.tag != IROP_TAG_IMM32 || src2.is_lval) return 0; + /* The ARM barrel-shift fusion pass records a hidden shift on an ALU op's + * src2 in ir->barrel_shifts[orig_index]. Later SSA folds can still make + * that visible src2 look like a plain immediate, but reassociating through + * it would combine constants as if the shift did not exist. */ + if (has_barrel_shift_annotation(ir, q)) + return 0; + /* src1 must be a single-use TEMP vreg */ int32_t src1_vr = irop_get_vreg(src1); if (src1_vr < 0 || TCCIR_DECODE_VREG_TYPE(src1_vr) != TCCIR_VREG_TYPE_TEMP) @@ -58,6 +72,8 @@ static int reassoc_binary(IRSSAOptCtx *ctx, int idx) return 0; IRQuadCompact *inner = &ir->compact_instructions[vi->def_instr]; + if (has_barrel_shift_annotation(ir, inner)) + return 0; /* Inner op must also have an immediate in src2 */ IROperand inner_src1 = tcc_ir_op_get_src1(ir, inner); @@ -195,6 +211,10 @@ static int reassoc_add_cancel_const(IRSSAOptCtx *ctx, int idx) IRQuadCompact *d1 = &ir->compact_instructions[vi1->def_instr]; IRQuadCompact *d2 = &ir->compact_instructions[vi2->def_instr]; + if (has_barrel_shift_annotation(ir, q) || + has_barrel_shift_annotation(ir, d1) || + has_barrel_shift_annotation(ir, d2)) + return 0; /* Match (a OP1 c) and (a OP2 c) where OP1/OP2 are {ADD, SUB} and the * constants cancel (same value with opposite signs in the combined sum). */ diff --git a/ir/opt_constfold.c b/ir/opt_constfold.c index 242d71fd..0fa40a9f 100644 --- a/ir/opt_constfold.c +++ b/ir/opt_constfold.c @@ -580,7 +580,16 @@ int tcc_ir_opt_self_copy_elim(TCCIRState *ir) !ir_opt_get_call_param_operand(ir, i, 1, &p1)) continue; - if (!ir_opt_pure_expr_equal(ir, p0, i, p1, i, 0)) + /* Resolve each param's source at its own marshalling site, not at the call + * index. If the source temp is redefined between param0 and param1, using + * the call index as the use-site for both collapses them to the same (last) + * reaching definition and the self-copy fold fires incorrectly. */ + int p0_idx = ir_opt_get_call_param_index(ir, i, 0); + int p1_idx = ir_opt_get_call_param_index(ir, i, 1); + if (p0_idx < 0 || p1_idx < 0) + continue; + + if (!ir_opt_pure_expr_equal(ir, p0, p0_idx, p1, p1_idx, 0)) continue; /* Self-copy: NOP the param marshalling and the call itself. @@ -1945,7 +1954,7 @@ static int rebuild_sim_env(const TCCFuncSwitchSnapshot *snap, int64_t arg_value, case TCCIR_OP_ADD: case TCCIR_OP_SUB: { - int64_t l, r1; + int64_t l = 0, r1 = 0; int rl = switch_sim_read_src(env, o, 1, &l); int rr = switch_sim_read_src(env, o, 2, &r1); if (rl == 0 || rr == 0) return 0; diff --git a/ir/opt_constprop.c b/ir/opt_constprop.c index 49c44598..278a13c8 100644 --- a/ir/opt_constprop.c +++ b/ir/opt_constprop.c @@ -2134,23 +2134,35 @@ static int tcc_ir_opt_const_prop__timed(TCCIRState *ir) result = (val1 != 0) || (val2 != 0) ? 1 : 0; break; case TCCIR_OP_IMOD: - if (val2 != 0) + if (val2 == 0) { - result = val1 % val2; + can_fold = 0; /* Division by zero - don't fold */ + } + else if (val2 == -1 && + ((btype == IROP_BTYPE_INT64 && val1 == INT64_MIN) || + (btype != IROP_BTYPE_INT64 && (int32_t)val1 == INT32_MIN))) + { + can_fold = 0; /* INT_MIN % -1 overflows in two's complement - bail */ } else { - can_fold = 0; /* Division by zero - don't fold */ + result = val1 % val2; } break; case TCCIR_OP_DIV: - if (val2 != 0) + if (val2 == 0) { - result = val1 / val2; + can_fold = 0; /* Division by zero - don't fold */ + } + else if (val2 == -1 && + ((btype == IROP_BTYPE_INT64 && val1 == INT64_MIN) || + (btype != IROP_BTYPE_INT64 && (int32_t)val1 == INT32_MIN))) + { + can_fold = 0; /* INT_MIN / -1 overflows in two's complement - bail */ } else { - can_fold = 0; /* Division by zero - don't fold */ + result = val1 / val2; } break; case TCCIR_OP_UDIV: @@ -6200,6 +6212,16 @@ int tcc_ir_opt_cmp_expr_fold(TCCIRState *ir) * const-var-prop may leave behind `CMP symref(X), symref(X)` that the * vreg-based path below would skip because vr1 == vr2 == -1. */ is_equal = ir_opt_nonvreg_expr_equal(ir, src1, src2); + /* Two integer immediates compare equal by value (e.g. `CMP #7, #7`). + * Scoped to the CMP-operand site (mirroring the asymmetric branch's + * manual check) rather than broadening the shared + * `ir_opt_nonvreg_expr_equal` helper, which would perturb its ADD/SUB + * base-equality callers. Floats excluded (NaN != NaN). */ + if (!is_equal && irop_is_immediate(src1) && irop_is_immediate(src2) && + !src1.is_sym && !src2.is_sym && + irop_get_btype(src1) != IROP_BTYPE_FLOAT32 && irop_get_btype(src1) != IROP_BTYPE_FLOAT64 && + irop_get_btype(src2) != IROP_BTYPE_FLOAT32 && irop_get_btype(src2) != IROP_BTYPE_FLOAT64) + is_equal = irop_get_imm64_ex(ir, src1) == irop_get_imm64_ex(ir, src2); /* Fallback for symref-vs-symref: the strict check requires every flag * to match, but the two operands at a CMP can carry different * unsigned/is_lval encodings from how the frontend lowered each side @@ -6290,7 +6312,7 @@ int tcc_ir_opt_cmp_expr_fold(TCCIRState *ir) } else { - if (vr1 < 0 || vr2 < 0 || vr1 == vr2) + if (vr1 < 0 || vr2 < 0) continue; /* Operand value-identity requires matching lval-ness: `*(p)` (a load @@ -6300,15 +6322,33 @@ int tcc_ir_opt_cmp_expr_fold(TCCIRState *ir) if (src1.is_lval != src2.is_lval) continue; - /* Both operands must have a single reaching definition */ - def1 = tcc_ir_find_defining_instruction(ir, vr1, i); - def2 = tcc_ir_find_defining_instruction(ir, vr2, i); - if (def1 < 0 || def2 < 0 || def1 == def2) - continue; + if (vr1 == vr2) + { + /* x OP x: a value compared against itself. CMP is an integer compare + * (floats lower to FCMP), so a plain register value is always + * determinate — evaluate_compare_condition(0,0,tok) gives the result. + * Require matching width and signedness: `CMP x:I8, x:I32` compares a + * truncation against the full value and is NOT always equal. A + * dereference *(V) OP *(V) could read a volatile location twice, so + * only fold the non-lval (register-value) form. */ + if (src1.is_lval || + irop_get_btype(src1) != irop_get_btype(src2) || + src1.is_unsigned != src2.is_unsigned) + continue; + is_equal = 1; + } + else + { + /* Both operands must have a single reaching definition */ + def1 = tcc_ir_find_defining_instruction(ir, vr1, i); + def2 = tcc_ir_find_defining_instruction(ir, vr2, i); + if (def1 < 0 || def2 < 0 || def1 == def2) + continue; - /* Try standard def equality (works for single-def vregs) */ - if (DC_IS_SINGLE_DEF(dc, dc_stride, vr1) && DC_IS_SINGLE_DEF(dc, dc_stride, vr2)) - is_equal = ir_opt_pure_def_equal(ir, def1, def2, 0); + /* Try standard def equality (works for single-def vregs) */ + if (DC_IS_SINGLE_DEF(dc, dc_stride, vr1) && DC_IS_SINGLE_DEF(dc, dc_stride, vr2)) + is_equal = ir_opt_pure_def_equal(ir, def1, def2, 0); + } } /* Pattern match: both defs are ADD/SUB with the same immediate, and @@ -7319,22 +7359,13 @@ int tcc_ir_opt_single_value_tmp(TCCIRState *ir) } if (changes) { - for (int i = 0; i < n; i++) { - IRQuadCompact *q = &ir->compact_instructions[i]; - if (q->op == TCCIR_OP_NOP || !irop_config[q->op].has_dest) - continue; - if (q->op != TCCIR_OP_ASSIGN && q->op != TCCIR_OP_LOAD) - continue; - IROperand d = tcc_ir_op_get_dest(ir, q); - int32_t dvr = irop_get_vreg(d); - if (dvr < 0 || TCCIR_DECODE_VREG_TYPE(dvr) != TCCIR_VREG_TYPE_TEMP) - continue; - int pos = TCCIR_DECODE_VREG_POSITION(dvr); - if (pos < count && state[pos] == 1) { - q->op = TCCIR_OP_NOP; - changes++; - } - } + /* Let DCE reclaim the now-dead constant defs. Do NOT NOP them directly by + * state[pos] == 1: a single-value temp may still have uses OTHER than the + * RETURNVALUE we just folded (e.g. `OR T, #const` in a bitfield store), + * because Phase 2 only propagates into RETURNVALUE operands. Blindly + * removing such a def leaves a dangling use → a use-before-def miscompile. + * DCE removes a def only when it has no remaining uses, which is exactly + * the condition we need. */ changes += tcc_ir_opt_dce(ir); } diff --git a/ir/opt_copyprop.c b/ir/opt_copyprop.c index 91af8d17..48a5238e 100644 --- a/ir/opt_copyprop.c +++ b/ir/opt_copyprop.c @@ -219,6 +219,13 @@ static int tcc_ir_opt_copy_prop__timed(TCCIRState *ir) LOG_COPY_PROP("Propagate src1 TMP:%d -> vreg:%d (lval=%d) at i=%d", pos, TCCIR_DECODE_VREG_POSITION(copy_info[pos].source_vr), src1.is_lval, i); tcc_ir_set_src1(ir, i, replacement); + /* Keep the local in sync so the copy-recording step below sees the + * propagated source, not the stale original. Otherwise an + * ASSIGN T2<-T1 rewritten to T2<-V0 is still recorded as T2<-V0's + * source = T1, leaving a T1 use that only collapses on a second pass + * (non-convergence). */ + src1 = replacement; + src1_vr = irop_get_vreg(replacement); changes++; } else @@ -256,6 +263,8 @@ static int tcc_ir_opt_copy_prop__timed(TCCIRState *ir) LOG_COPY_PROP("Propagate src2 TMP:%d -> vreg:%d (lval=%d) at i=%d", pos, TCCIR_DECODE_VREG_POSITION(copy_info[pos].source_vr), src2.is_lval, i); tcc_ir_set_src2(ir, i, replacement); + src2 = replacement; + src2_vr = irop_get_vreg(replacement); changes++; } } @@ -381,7 +390,7 @@ static int tcc_ir_opt_copy_prop__timed(TCCIRState *ir) (db != IROP_BTYPE_INT64 && db != IROP_BTYPE_FLOAT32 && db != IROP_BTYPE_FLOAT64 && sb != IROP_BTYPE_INT64 && sb != IROP_BTYPE_FLOAT32 && sb != IROP_BTYPE_FLOAT64 && db != IROP_BTYPE_INT8 && db != IROP_BTYPE_INT16 && sb != IROP_BTYPE_INT8 && sb != IROP_BTYPE_INT16); - if (!src_is_const && src1_vr >= 0 && !src1.is_lval && btype_compat && + if (!src_is_const && src1_vr >= 0 && src1_vr != dest_vr && !src1.is_lval && btype_compat && (src_vreg_type == TCCIR_VREG_TYPE_VAR || src_vreg_type == TCCIR_VREG_TYPE_PARAM || src_vreg_type == TCCIR_VREG_TYPE_TEMP)) { diff --git a/ir/opt_dead_lea_store.c b/ir/opt_dead_lea_store.c index 6e5eccdb..e7871ccc 100644 --- a/ir/opt_dead_lea_store.c +++ b/ir/opt_dead_lea_store.c @@ -526,6 +526,69 @@ int tcc_ir_opt_dead_lea_store_elim(TCCIRState *ir) if (dest.is_complex) dest_w *= 2; int store_off = slot_off; + + /* Write-after-write: if a later store in the same straight-line run fully + * overwrites this store's byte range with no read of those bytes in + * between, S1's value is never observed — eliminate it even though the slot + * is read further on (that read sees the overwriting store's value). + * Restricting to a straight-line run (break at any control-flow op or jump + * target) keeps the proof sound: the covering store unconditionally runs + * after S1 before any branch could route to a read. Intermediate stores + * never *read* R1 (their value operands were escape-checked in Pass 2), so + * they cannot keep S1 alive — only a recorded read can. */ + int waw_dead = 0; + for (int j = i + 1; j < n; j++) + { + IRQuadCompact *qj = &ir->compact_instructions[j]; + if (qj->op == TCCIR_OP_NOP) + continue; + if (qj->is_jump_target) + break; /* control-flow merge — straight-line run ends */ + if (qj->op == TCCIR_OP_JUMP || qj->op == TCCIR_OP_JUMPIF || + qj->op == TCCIR_OP_IJUMP || qj->op == TCCIR_OP_SWITCH_TABLE || + qj->op == TCCIR_OP_RETURNVALUE || qj->op == TCCIR_OP_RETURNVOID || + qj->op == TCCIR_OP_FUNCCALLVAL || qj->op == TCCIR_OP_FUNCCALLVOID) + break; /* leaves the straight-line run */ + if (qj->op != TCCIR_OP_STORE) + continue; + IROperand d2 = tcc_ir_op_get_dest(ir, qj); + if (!RESOLVE_LVAL_SLOT(d2)) + continue; /* writes a non-tracked location (no escapes survived Pass 2) */ + int off2 = slot_off; + int w2 = ir_opt_store_btype_size_bytes(irop_get_btype(d2)); + if (w2 <= 0) + w2 = irop_is_64bit(d2) ? 8 : 4; + if (d2.is_complex) + w2 *= 2; + if (off2 <= store_off && store_off + dest_w <= off2 + w2) + { + /* Full cover: S1 is dead unless its bytes are read before j. */ + int read_between = 0; + for (int r = 0; r < reads_n; r++) + if (store_off < reads[r].off + reads[r].width && + reads[r].off < store_off + dest_w && + reads[r].pos > i && reads[r].pos < j) + { + read_between = 1; + break; + } + if (!read_between) + waw_dead = 1; + break; + } + if (store_off < off2 + w2 && off2 < store_off + dest_w) + break; /* partial overlap — cannot prove S1 fully dead */ + /* disjoint slot — keep scanning for a covering store */ + } + if (waw_dead) + { + LOG_IR_GEN("DEAD LEA-STORE (WAW): nop STORE to StackLoc[%d] at i=%d w=%d", + store_off, i, dest_w); + q->op = TCCIR_OP_NOP; + changes++; + continue; + } + int alive = 0; for (int r = 0; r < reads_n; r++) { diff --git a/ir/opt_fusion.c b/ir/opt_fusion.c index 1bd0dab8..69ecc443 100644 --- a/ir/opt_fusion.c +++ b/ir/opt_fusion.c @@ -1433,6 +1433,8 @@ void tcc_ir_barrel_shift_fusion(TCCIRState *ir) IROperand other = (attempt == 0) ? tcc_ir_op_get_src1(ir, q) : tcc_ir_op_get_src2(ir, q); + if (!irop_has_vreg(other)) + continue; if (irop_has_vreg(other) && irop_get_vreg(other) == shift_src_vr) continue; @@ -2992,4 +2994,3 @@ int tcc_ir_opt_assign_fuse(TCCIRState *ir) int tcc_ir_opt_postinc_fusion_ex(IROptCtx *ctx) { return tcc_ir_opt_postinc_fusion(ctx->ir); } int tcc_ir_opt_assign_fuse_ex(IROptCtx *ctx) { return tcc_ir_opt_assign_fuse(ctx->ir); } - diff --git a/ir/opt_knownbits.c b/ir/opt_knownbits.c index 967e7d52..8b088531 100644 --- a/ir/opt_knownbits.c +++ b/ir/opt_knownbits.c @@ -424,7 +424,7 @@ static IROperand kb_make_const_operand(TCCIRState *ir, uint64_t val, int btype) return irop_make_i64(-1, pool_idx, btype); } -static int kb_const_compute(TccIrOp op, int dest_btype, +static int kb_const_compute(TccIrOp op, int dest_btype, int src1_btype, uint64_t a, uint64_t b, uint64_t *out) { int width = (dest_btype == IROP_BTYPE_INT64) ? 64 : 32; @@ -434,9 +434,24 @@ static int kb_const_compute(TccIrOp op, int dest_btype, { case TCCIR_OP_ASSIGN: case TCCIR_OP_LOAD: - case TCCIR_OP_ZEXT: *out = a; break; + case TCCIR_OP_ZEXT: + { + /* Zero-extend from the SOURCE width. kb_operand_const_u64 sign-extends a + * signed source to 64 bits, so a verbatim copy would poison the high half + * (e.g. ZEXT(#-326:I32) must give 0x00000000FFFFFEBA, not ...FFFFFEBA). */ + uint64_t src_mask; + switch (src1_btype) + { + case IROP_BTYPE_INT8: src_mask = 0xFFULL; break; + case IROP_BTYPE_INT16: src_mask = 0xFFFFULL; break; + case IROP_BTYPE_INT32: src_mask = 0xFFFFFFFFULL; break; + default: src_mask = ~0ULL; break; + } + *out = a & src_mask; + break; + } case TCCIR_OP_ADD: *out = a + b; break; @@ -460,7 +475,9 @@ static int kb_const_compute(TccIrOp op, int dest_btype, case TCCIR_OP_SHR: if (b >= (uint64_t)width) return 0; - *out = a >> b; + /* Logical shift: mask the source to the operation width first so the + * sign-extended high bits (for a 32-bit op) are not shifted in. */ + *out = (a & mask) >> b; break; case TCCIR_OP_SAR: if (b >= (uint64_t)width) @@ -1224,7 +1241,7 @@ static int tcc_ir_opt_known_bits__timed(TCCIRState *ir) var_addr, max_var_pos, stack_slots, n_stack_slots, &cv2); if (h1 && (!irop_config[op].has_src2 || h2) && - kb_const_compute(op, dest_btype, cv1, cv2, &cres)) + kb_const_compute(op, dest_btype, s1_btype, cv1, cv2, &cres)) { IROperand imm = kb_make_const_operand(ir, cres, dest_btype); imm.is_unsigned = dest.is_unsigned; diff --git a/ir/opt_loop.c b/ir/opt_loop.c index bd97c8a2..978f5b16 100644 --- a/ir/opt_loop.c +++ b/ir/opt_loop.c @@ -562,6 +562,12 @@ int tcc_ir_opt_loop_bound_remat(TCCIRState *ir) static int tcc_ir_opt_loop_unroll__timed(TCCIRState *ir); int tcc_ir_opt_loop_unroll(TCCIRState *ir) { + /* Finding #15: random-C differential seed 18 still exposes O2-only + * wrong-code through the loop unroller. Keep the pass disabled until the + * relocation/live-range handling is repaired; correctness beats the small + * code-size/speed win here. */ + (void)ir; + return 0; tcc_pass_timing_init(); if (!tcc_pass_timing_on) return tcc_ir_opt_loop_unroll__timed(ir); unsigned long _t = tcc_pass_clk_us(); @@ -734,6 +740,11 @@ static int tcc_ir_opt_loop_unroll__timed(TCCIRState *ir) static int tcc_ir_opt_loop_rotation__timed(TCCIRState *ir); int tcc_ir_opt_loop_rotation(TCCIRState *ir) { + /* Finding #15: loop rotation miscompiles O2 random-C checksum loops over + * local arrays (seeds 23 and 37). Disable the transform until its body + * relocation and downstream forwarding/coalescing invariants are fixed. */ + (void)ir; + return 0; tcc_pass_timing_init(); if (!tcc_pass_timing_on) return tcc_ir_opt_loop_rotation__timed(ir); unsigned long _t = tcc_pass_clk_us(); diff --git a/ir/opt_loop_utils.c b/ir/opt_loop_utils.c index 3cac3b8d..1ab00ac6 100644 --- a/ir/opt_loop_utils.c +++ b/ir/opt_loop_utils.c @@ -3569,6 +3569,26 @@ int try_rotate_loop(TCCIRState *ir, IRLoop *loop) if (body_count > 128) return 0; + /* Calls inside the rotated body make the carried live ranges cross a + * different control-flow shape after rotation. Later forwarding/coalescing + * can then observe the preheader/body copies as interchangeable when the + * call-clobbered value is not. Keep call-containing loops in their original + * top-tested form; simple call-free counted loops still rotate. */ + for (int i = body_start; i <= body_end; i++) + { + int op = ir->compact_instructions[i].op; + if (op == TCCIR_OP_FUNCCALLVAL || op == TCCIR_OP_FUNCCALLVOID) + { + LOG_LOOP_OPT("Rotation: reject — body has call at %d", i); + return 0; + } + if (op == TCCIR_OP_LOAD_INDEXED || op == TCCIR_OP_STORE_INDEXED) + { + LOG_LOOP_OPT("Rotation: reject — body has indexed memory op at %d", i); + return 0; + } + } + /* --- Step 4a2: Reject if body has a fall-through exit --- */ /* When body_end_is_implicit, the body may end with trailing NOPs (from * eliminated fall-through jumps) after a JUMPIF. In the original layout, @@ -4008,4 +4028,3 @@ int loop_size_cmp(const void *a, const void *b) int sb = lb->end_idx - lb->start_idx; return sa - sb; } - diff --git a/ir/opt_memory.c b/ir/opt_memory.c index 6113fdc8..7344f6da 100644 --- a/ir/opt_memory.c +++ b/ir/opt_memory.c @@ -4106,8 +4106,13 @@ static void rse_build_def_map(TCCIRState *ir) max_pos = p; } } - rse_def_map_size = max_pos + 1; + /* Release any map left over from an earlier build before overwriting the + * pointer. tcc_ir_opt_const_memcpy_to_dest rebuilds the map after every + * successful rewrite, so without this the previous allocation would leak + * (tcc_free(NULL) is a no-op on the first/clean call). */ + tcc_free(rse_def_map); rse_def_map = NULL; + rse_def_map_size = max_pos + 1; if (rse_def_map_size <= 0) return; rse_def_map = (int *)tcc_malloc(sizeof(int) * rse_def_map_size); diff --git a/ir/opt_neg_chain.c b/ir/opt_neg_chain.c index b003be5b..191573ad 100644 --- a/ir/opt_neg_chain.c +++ b/ir/opt_neg_chain.c @@ -154,7 +154,11 @@ int tcc_ir_opt_neg_chain_cse(TCCIRState *ir) { IROperand src1 = tcc_ir_op_get_src1(ir, q); int32_t src_vr = irop_get_vreg(src1); - if (!src1.is_lval && src_vr >= 0 && TCCIR_DECODE_VREG_TYPE(src_vr) == TCCIR_VREG_TYPE_TEMP) + /* Width must match for the copy to be value-preserving — an ASSIGN that + * narrows/widens (e.g. T_b:I8 <- T_a:I32) does not carry T_a's full value, + * so it must anchor to itself rather than join T_a's canonical chain. */ + if (!src1.is_lval && src_vr >= 0 && TCCIR_DECODE_VREG_TYPE(src_vr) == TCCIR_VREG_TYPE_TEMP && + irop_get_btype(dest) == irop_get_btype(src1)) { int src_pos = TCCIR_DECODE_VREG_POSITION(src_vr); if (src_pos <= max_tmp && canon[src_pos].valid) @@ -173,8 +177,19 @@ int tcc_ir_opt_neg_chain_cse(TCCIRState *ir) { IROperand src1 = tcc_ir_op_get_src1(ir, q); IROperand src2 = tcc_ir_op_get_src2(ir, q); - /* Match the negation idiom: T_b = #0 SUB T_a. */ - if (irop_is_immediate(src1) && irop_get_imm64_ex(ir, src1) == 0) + int dest_btype = irop_get_btype(dest); + int src_btype = irop_get_btype(src2); + /* Match the negation idiom: T_b = #0 SUB T_a. + * + * Width must match — a width-changing negation (e.g. T_b:I8 = -T_a:I32) + * truncates, so it is NOT value-preserving and must NOT join T_a's + * canonical chain. Were it recorded as "T_b = -base" against the wider + * base, a later same-width negation could be folded straight back to the + * wide base, dropping the truncation and miscompiling. When the widths + * differ the dest anchors to itself (base = dest, sign = +) via the + * defaults above, keeping first_pos/first_neg homogeneous per base. */ + if (irop_is_immediate(src1) && irop_get_imm64_ex(ir, src1) == 0 && + dest_btype == src_btype) { int32_t src_vr = irop_get_vreg(src2); if (!src2.is_lval && src_vr >= 0 && TCCIR_DECODE_VREG_TYPE(src_vr) == TCCIR_VREG_TYPE_TEMP) @@ -191,27 +206,20 @@ int tcc_ir_opt_neg_chain_cse(TCCIRState *ir) sign = 1; } - /* Width must match — otherwise an ASSIGN of a different-width TEMP - * could drop or extend bits the SUB wouldn't have. */ - int dest_btype = irop_get_btype(dest); - int src_btype = irop_get_btype(src2); - if (dest_btype == src_btype) + int base_pos = TCCIR_DECODE_VREG_POSITION(base_vr); + int32_t existing = (sign == 1) ? first_neg[base_pos] : first_pos[base_pos]; + if (existing >= 0 && existing != dest_vr) { - int base_pos = TCCIR_DECODE_VREG_POSITION(base_vr); - int32_t existing = (sign == 1) ? first_neg[base_pos] : first_pos[base_pos]; - if (existing >= 0 && existing != dest_vr) - { - IROperand new_src = irop_make_vreg(existing, dest_btype); - q->op = TCCIR_OP_ASSIGN; - tcc_ir_set_src1(ir, i, new_src); - tcc_ir_set_src2(ir, i, IROP_NONE); - LOG_NEG_CHAIN("@%d: T%d = -T%d folded to T%d = T%d (base=T%d sign=%d)", - i, dest_pos, TCCIR_DECODE_VREG_POSITION(src_vr), - dest_pos, TCCIR_DECODE_VREG_POSITION(existing), - base_pos, sign); - changes++; - did_replace = 1; - } + IROperand new_src = irop_make_vreg(existing, dest_btype); + q->op = TCCIR_OP_ASSIGN; + tcc_ir_set_src1(ir, i, new_src); + tcc_ir_set_src2(ir, i, IROP_NONE); + LOG_NEG_CHAIN("@%d: T%d = -T%d folded to T%d = T%d (base=T%d sign=%d)", + i, dest_pos, TCCIR_DECODE_VREG_POSITION(src_vr), + dest_pos, TCCIR_DECODE_VREG_POSITION(existing), + base_pos, sign); + changes++; + did_replace = 1; } } } diff --git a/ir/opt_utils.c b/ir/opt_utils.c index 937248fa..0467bb60 100644 --- a/ir/opt_utils.c +++ b/ir/opt_utils.c @@ -1068,6 +1068,43 @@ int ir_opt_get_call_param_operand(TCCIRState *ir, int call_idx, int param_idx, I return 0; } +int ir_opt_get_call_param_index(TCCIRState *ir, int call_idx, int param_idx) +{ + IRQuadCompact *call_q; + IROperand call_src2; + int call_id; + + if (!ir || call_idx < 0 || call_idx >= ir->next_instruction_index) + return -1; + + call_q = &ir->compact_instructions[call_idx]; + if (call_q->op != TCCIR_OP_FUNCCALLVAL && call_q->op != TCCIR_OP_FUNCCALLVOID) + return -1; + + call_src2 = tcc_ir_op_get_src2(ir, call_q); + call_id = TCCIR_DECODE_CALL_ID((uint32_t)irop_get_imm64_ex(ir, call_src2)); + + for (int i = call_idx - 1; i >= 0; --i) + { + IRQuadCompact *q = &ir->compact_instructions[i]; + if (q->op == TCCIR_OP_NOP) + continue; + if (q->op != TCCIR_OP_FUNCPARAMVAL && q->op != TCCIR_OP_FUNCPARAMVOID) + continue; + + IROperand enc = tcc_ir_op_get_src2(ir, q); + uint32_t encoded = (uint32_t)irop_get_imm64_ex(ir, enc); + if (TCCIR_DECODE_CALL_ID(encoded) != call_id) + continue; + if (TCCIR_DECODE_PARAM_IDX(encoded) != param_idx) + continue; + + return i; + } + + return -1; +} + void ir_opt_nop_call_params(TCCIRState *ir, int call_idx) { IRQuadCompact *call_q; @@ -1233,6 +1270,8 @@ int change_callee_sym(TCCIRState *ir, int instr_idx, const char *new_name, int r CType ftype; ftype.t = VT_FUNC; ftype.ref = sym_push2(&global_stack, SYM_FIELD, ret_btype, 0); + if (!ftype.ref) + return 0; /* out of symbols — leave the callee unchanged rather than crash */ ftype.ref->f.func_call = FUNC_CDECL; ftype.ref->f.func_type = FUNC_OLD; diff --git a/ir/opt_utils.h b/ir/opt_utils.h index 4628a838..310efa59 100644 --- a/ir/opt_utils.h +++ b/ir/opt_utils.h @@ -86,6 +86,12 @@ int ir_opt_pure_expr_equal(struct TCCIRState *ir, IROperand a, int a_use_idx, int ir_opt_get_call_param_operand(struct TCCIRState *ir, int call_idx, int param_idx, IROperand *out); +/* Instruction index of the FUNCPARAMVAL/FUNCPARAMVOID marshalling `param_idx` + * for the call at `call_idx`, or -1. Use this as the reaching-def use-site for + * a param's source: the call index is wrong because the source may be redefined + * between param marshalling and the call. */ +int ir_opt_get_call_param_index(struct TCCIRState *ir, int call_idx, + int param_idx); void ir_opt_nop_call_params(struct TCCIRState *ir, int call_idx); void ir_opt_nop_call_param(struct TCCIRState *ir, int call_idx, int param_idx); void ir_opt_change_call_argc(struct TCCIRState *ir, int call_idx, int argc); diff --git a/ir/regalloc.c b/ir/regalloc.c index 27c22607..56cbbca7 100644 --- a/ir/regalloc.c +++ b/ir/regalloc.c @@ -3364,8 +3364,20 @@ static void ra_resolve_phis(TCCIRState *ir, IRCFG *cfg, IRSSAState *ssa) * builder (it tries to extend phi-dest intervals as if the phi were * still semantically active, on top of the now-explicit defs). */ if (ra_phi_resolve_pre_ra_mode) { - for (int b = 0; b < nb; b++) + /* Free each block's phi list before detaching it — the explicit copies are + * now the source of truth, so these nodes are dead. Merely NULLing the + * heads (as before) orphaned every phi node + operand array: tcc_ir_ssa_free + * later sees an empty block_phis and frees nothing, leaking on every compile. */ + for (int b = 0; b < nb; b++) { + IRPhiNode *phi = ssa->block_phis[b]; + while (phi) { + IRPhiNode *next = phi->next; + tcc_free(phi->operands); + tcc_free(phi); + phi = next; + } ssa->block_phis[b] = NULL; + } tcc_free(old_to_new); tcc_free(copies_per_block); tcc_free(copy_records); @@ -4002,24 +4014,33 @@ void tcc_ir_ssa_regalloc(TCCIRState *ir, const RegAllocTarget *target, int spill if (had_promotable) { tcc_ir_ssa_opt_run(&ssa_opt_ctx); } else { + /* Run a pass, then make it observable to -dump-ir-passes= + * golden snapshots (same names as the tcc_ir_ssa_opt_run driver). */ +#define RUN_SSA(name, call) \ + do \ + { \ + (call); \ + tcc_ir_dump_after_pass(ir, name); \ + } while (0) ssa_opt_ctx.no_stack_fwd = 0; - ssa_opt_var_const_fold(&ssa_opt_ctx); - ssa_opt_var_forward(&ssa_opt_ctx); - ssa_opt_sccp(&ssa_opt_ctx); - ssa_opt_load_cse(&ssa_opt_ctx); - ssa_opt_cprop(&ssa_opt_ctx); - ssa_opt_fold(&ssa_opt_ctx); - ssa_opt_branch(&ssa_opt_ctx); - ssa_opt_reassoc(&ssa_opt_ctx); - ssa_opt_strength(&ssa_opt_ctx); - ssa_opt_narrow(&ssa_opt_ctx); - ssa_opt_gvn(&ssa_opt_ctx); - ssa_opt_phi_simplify(&ssa_opt_ctx); - ssa_opt_dce(&ssa_opt_ctx); + RUN_SSA("ssa:var_const_fold", ssa_opt_var_const_fold(&ssa_opt_ctx)); + RUN_SSA("ssa:var_forward", ssa_opt_var_forward(&ssa_opt_ctx)); + RUN_SSA("ssa:sccp", ssa_opt_sccp(&ssa_opt_ctx)); + RUN_SSA("ssa:load_cse", ssa_opt_load_cse(&ssa_opt_ctx)); + RUN_SSA("ssa:cprop", ssa_opt_cprop(&ssa_opt_ctx)); + RUN_SSA("ssa:fold", ssa_opt_fold(&ssa_opt_ctx)); + RUN_SSA("ssa:branch", ssa_opt_branch(&ssa_opt_ctx)); + RUN_SSA("ssa:reassoc", ssa_opt_reassoc(&ssa_opt_ctx)); + RUN_SSA("ssa:strength", ssa_opt_strength(&ssa_opt_ctx)); + RUN_SSA("ssa:narrow", ssa_opt_narrow(&ssa_opt_ctx)); + RUN_SSA("ssa:gvn", ssa_opt_gvn(&ssa_opt_ctx)); + RUN_SSA("ssa:phi_simplify", ssa_opt_phi_simplify(&ssa_opt_ctx)); + RUN_SSA("ssa:dce", ssa_opt_dce(&ssa_opt_ctx)); /* Target-specific fusions (MLA, LOAD/STORE_INDEXED on ARM). These * don't need promotable vars or phi nodes — they pattern-match on * existing TEMP vregs. */ tcc_ir_ssa_opt_run_target(&ssa_opt_ctx); +#undef RUN_SSA } } else { ssa_opt_cprop(&ssa_opt_ctx); diff --git a/scripts/asan_sweep.py b/scripts/asan_sweep.py new file mode 100755 index 00000000..c7ec4bdd --- /dev/null +++ b/scripts/asan_sweep.py @@ -0,0 +1,341 @@ +#!/usr/bin/env python3 +""" +asan_sweep.py — corpus enumeration + sweep driver + dedup/report for the +tinycc ASAN/UBSan bug-hunting sweep (Phase BH, Track 1). + +This is a *helper* invoked by scripts/asan_sweep.sh; the bash script remains the +entry point. It exists because robust corpus enumeration (gcc-torture builtins +source expansion, shardable file lists), per-file compile invocation, sanitizer +signature detection and stack-frame dedup are far cleaner in Python than in bash. + +The oracle is the sanitizer output printed by `armv8m-tcc` (built with +-fsanitize=address by default). An ordinary "unsupported feature" compile error +(nonzero exit, no sanitizer line) is NOT a hit; only a real sanitizer report is. + +Test/tooling only. Does not modify production code or config.mak. +""" + +import argparse +import os +import re +import subprocess +import sys +from pathlib import Path + +REPO = Path(__file__).resolve().parent.parent + +# Sanitizer signatures that mark a genuine hit. We deliberately key on the +# sanitizer's own markers, NOT on the compiler exit code (a plain "unsupported +# feature" error also exits nonzero but prints none of these). +SANITIZER_RE = re.compile( + r"(ERROR: AddressSanitizer" + r"|ERROR: LeakSanitizer" + r"|LeakSanitizer: detected memory leaks" + r"|runtime error:" # UBSan + r"|SUMMARY: .*Sanitizer)" +) + +# A SUMMARY line is the most human-readable one-liner for the report. +SUMMARY_RE = re.compile(r"SUMMARY: .*?Sanitizer:.*") +# UBSan runtime errors do not always emit a SUMMARY; capture the first one. +UBSAN_RE = re.compile(r".*runtime error:.*") + +# Backtrace frame: " #3 0x... in (...)" +FRAME_RE = re.compile(r"#\d+\s+0x[0-9a-f]+\s+in\s+(\S+)") + +# Generic allocator / wrapper / runtime frames that are NOT the root cause and +# must be skipped when building a dedup key (otherwise every leak collapses into +# one bucket regardless of where it was actually allocated). +NOISE_FRAMES = { + "malloc", "calloc", "realloc", "free", "reallocarray", + "realloc.part.0", "malloc.part.0", + "operator new", "operator new[]", + "default_reallocator", "default_realloc", + "tcc_malloc", "tcc_mallocz", "tcc_realloc", "tcc_realloc_debug", + "tcc_malloc_debug", "tcc_mallocz_debug", "tcc_free", "tcc_strdup", + "__interceptor_malloc", "__interceptor_calloc", "__interceptor_realloc", + "__libc_start_main", "__libc_start_call_main", "_start", "main", + "__asan_memcpy", "__asan_memset", "__asan_memmove", + "__sanitizer_print_stack_trace", +} + + +def _is_noise(sym): + if sym in NOISE_FRAMES: + return True + # libasan internal frames have no real symbol of interest. + if sym.startswith("__asan_") or sym.startswith("__ubsan_") or sym.startswith("__lsan_"): + return True + if sym.startswith("__interceptor_"): + return True + return False + + +def meaningful_frames(stderr_text, k=3): + """Return the first k meaningful (non-noise) backtrace symbols across the + whole report, in order. This is the dedup key — the same bug across many + files collapses to a single entry.""" + frames = [] + for m in FRAME_RE.finditer(stderr_text): + sym = m.group(1) + if _is_noise(sym): + continue + frames.append(sym) + if len(frames) >= k: + break + return frames + + +def summary_line(stderr_text): + m = SUMMARY_RE.search(stderr_text) + if m: + return m.group(0).strip() + m = UBSAN_RE.search(stderr_text) + if m: + return m.group(0).strip()[:200] + # Fall back to the ERROR line. + for line in stderr_text.splitlines(): + if "Sanitizer" in line and ("ERROR" in line or "WARNING" in line): + return line.strip() + return "Sanitizer report (no SUMMARY line)" + + +# -------------------------------------------------------------------------- +# Corpus enumeration +# -------------------------------------------------------------------------- + +def _gcc_torture_root(): + return REPO / "tests/gcctestsuite/gcc-testsuite/gcc/testsuite/gcc.c-torture" + + +def expand_gcc_builtin_sources(source): + """Mirror tests/ir_tests/run.py:expand_gcc_builtin_sources — a builtins/ + execute test needs its -lib.c companion plus lib/main.c so the + compile actually exercises the same multi-TU shape the real harness uses.""" + extra = [] + if source.name.endswith("-lib.c"): + return extra + parent = source.parent + if parent.name != "builtins": + return extra + if parent.parent.name != "execute": + return extra + if parent.parent.parent.name != "gcc.c-torture": + return extra + lib_file = source.with_name(f"{source.stem}-lib.c") + builtins_main = parent / "lib" / "main.c" + for f in (lib_file, builtins_main): + if f.exists(): + extra.append(f) + return extra + + +def enumerate_corpus(corpus): + """Return a list of (primary_source: Path, extra_sources: [Path]) work items.""" + items = [] + + def add_gcc_torture(): + root = _gcc_torture_root() + if not root.exists(): + print(f"warning: gcc-torture not found at {root} " + f"(run 'make download-gcc-tests')", file=sys.stderr) + return + execute = root / "execute" + # Top-level + ieee + builtins, recursively; skip -lib.c companions and + # files inside lib/ (they are pulled in as extra sources, not compiled + # standalone). + for c in sorted(execute.rglob("*.c")): + if c.name.endswith("-lib.c"): + continue + if c.parent.name == "lib": + continue + items.append((c, expand_gcc_builtin_sources(c))) + compile_dir = root / "compile" + if compile_dir.exists(): + for c in sorted(compile_dir.glob("*.c")): + items.append((c, [])) + + if corpus in ("gcc-torture", "all"): + add_gcc_torture() + if corpus in ("tests2", "all"): + for c in sorted((REPO / "tests/tests2").glob("*.c")): + items.append((c, [])) + if corpus in ("ir_tests", "all"): + for c in sorted((REPO / "tests/ir_tests").glob("*.c")): + items.append((c, [])) + + return items + + +def apply_shard_limit(items, shard, limit): + if shard: + i, n = shard + items = [it for idx, it in enumerate(items) if idx % n == (i - 1)] + if limit: + items = items[:limit] + return items + + +# -------------------------------------------------------------------------- +# Compile +# -------------------------------------------------------------------------- + +def build_compile_cmd(compiler, include_flags, abi_flags, opt, sources): + cmd = [str(compiler), f"-B{REPO}"] + cmd += abi_flags + cmd += include_flags + cmd += [opt, "-c"] + cmd += [str(s) for s in sources] + cmd += ["-o", "/dev/null"] + return cmd + + +def run_one(compiler, include_flags, abi_flags, opt, primary, extras, timeout): + sources = [primary] + list(extras) + cmd = build_compile_cmd(compiler, include_flags, abi_flags, opt, sources) + try: + proc = subprocess.run( + cmd, + stdout=subprocess.DEVNULL, + stderr=subprocess.PIPE, + timeout=timeout, + ) + stderr = proc.stderr.decode("utf-8", errors="replace") + rc = proc.returncode + except subprocess.TimeoutExpired as e: + stderr = (e.stderr or b"").decode("utf-8", errors="replace") + rc = -1 + return rc, stderr + + +def main(): + ap = argparse.ArgumentParser(description=__doc__) + ap.add_argument("--compiler", default=str(REPO / "armv8m-tcc"), + help="path to the cross compiler (ASAN-built armv8m-tcc)") + ap.add_argument("--corpus", default="all", + choices=["gcc-torture", "tests2", "ir_tests", "all"]) + ap.add_argument("--olevels", default="-O0,-O1,-O2", + help="comma-separated optimization levels") + ap.add_argument("--shard", default=None, + help="i/N — sweep only shard i of N (1-based)") + ap.add_argument("--limit", type=int, default=0, + help="cap number of files swept (after sharding)") + ap.add_argument("--timeout", type=int, default=60, + help="per-compile timeout in seconds") + ap.add_argument("--include-flags", default="", + help="space-separated -I flags from the harness Makefile") + ap.add_argument("--abi-flags", default="", + help="space-separated ABI/codegen flags from the Makefile") + ap.add_argument("--report", default=None, + help="write the deduped report here (also printed to stdout)") + ap.add_argument("--list-hits-raw", default=None, + help="append every raw hit line (file|olevel|key) here") + ap.add_argument("--progress-every", type=int, default=100) + args = ap.parse_args() + + shard = None + if args.shard: + i, n = args.shard.split("/") + shard = (int(i), int(n)) + if not (1 <= shard[0] <= shard[1]): + print(f"error: bad shard {args.shard}", file=sys.stderr) + return 2 + + olevels = [o.strip() for o in args.olevels.split(",") if o.strip()] + include_flags = args.include_flags.split() + abi_flags = args.abi_flags.split() + + items = enumerate_corpus(args.corpus) + total_files = len(items) + items = apply_shard_limit(items, shard, args.limit) + + compiler = Path(args.compiler) + if not compiler.exists(): + print(f"error: compiler not found: {compiler}", file=sys.stderr) + return 2 + + # bug_key -> dict(summary, key_frames, count, repros=[(file, olevel)]) + bugs = {} + swept = 0 + hit_compiles = 0 + raw_hits = [] + + for idx, (primary, extras) in enumerate(items): + for opt in olevels: + swept += 1 + rc, stderr = run_one(compiler, include_flags, abi_flags, + opt, primary, extras, args.timeout) + if not SANITIZER_RE.search(stderr): + continue + hit_compiles += 1 + frames = meaningful_frames(stderr, k=3) + key = " <- ".join(frames) if frames else "(no meaningful frames)" + summ = summary_line(stderr) + rel = os.path.relpath(primary, REPO) + raw_hits.append(f"{rel}|{opt}|{key}") + b = bugs.setdefault(key, { + "summary": summ, + "frames": frames, + "count": 0, + "repro": None, + "files": set(), + }) + b["count"] += 1 + b["files"].add(rel) + if b["repro"] is None: + b["repro"] = (rel, opt) + # Prefer the most informative summary if a later one is richer. + if summ and len(summ) > len(b["summary"]): + b["summary"] = summ + if args.progress_every and (idx + 1) % args.progress_every == 0: + print(f" ... {idx + 1}/{len(items)} files, " + f"{len(bugs)} unique bug(s)", file=sys.stderr) + + # ---- report ---- + lines = [] + lines.append("=" * 78) + lines.append("ASAN/UBSan sweep report") + lines.append("=" * 78) + lines.append(f"corpus : {args.corpus}") + lines.append(f"olevels : {','.join(olevels)}") + if shard: + lines.append(f"shard : {shard[0]}/{shard[1]}") + if args.limit: + lines.append(f"limit : {args.limit}") + lines.append(f"files in corpus : {total_files}") + lines.append(f"files this run : {len(items)}") + lines.append(f"compiles run : {swept}") + lines.append(f"sanitizer hits : {hit_compiles} compile(s)") + lines.append(f"unique bugs : {len(bugs)}") + lines.append("") + + if bugs: + # Sort by count descending so the most-frequent bug is first. + for n, (key, b) in enumerate( + sorted(bugs.items(), key=lambda kv: -kv[1]["count"]), 1): + repro_file, repro_opt = b["repro"] + lines.append(f"[BUG {n}] {key}") + lines.append(f" summary : {b['summary']}") + lines.append(f" seen in : {b['count']} compile(s) " + f"across {len(b['files'])} file(s)") + lines.append(f" repro : {repro_file} {repro_opt}") + lines.append("") + else: + lines.append("No sanitizer hits in this slice.") + lines.append("") + + report = "\n".join(lines) + print(report) + + if args.report: + Path(args.report).write_text(report) + if args.list_hits_raw and raw_hits: + with open(args.list_hits_raw, "a") as f: + for h in raw_hits: + f.write(h + "\n") + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/scripts/asan_sweep.sh b/scripts/asan_sweep.sh new file mode 100755 index 00000000..4d9639c7 --- /dev/null +++ b/scripts/asan_sweep.sh @@ -0,0 +1,175 @@ +#!/usr/bin/env bash +# +# asan_sweep.sh — Phase BH / Track 1 ASAN+UBSan corpus sweep for tinycc. +# +# The cross compiler armv8m-tcc is built with AddressSanitizer ON by default +# (config.mak: -fsanitize=address), so compiling any corpus file *with* it makes +# tcc report ASAN/LeakSanitizer errors on its OWN heap bugs. The ORACLE is the +# sanitizer output printed by tcc, not the compile exit code: a plain +# "unsupported feature" compile error is NOT a hit. +# +# This sweeps the corpus (gcc-torture compile+execute, tests2, ir_tests) across +# -O0/-O1/-O2, greps stderr for sanitizer signatures, and dedups hits by the top +# meaningful backtrace frames so one bug across many files collapses to one entry. +# +# Test/tooling only. Does NOT modify production code. --with-ubsan builds a +# SEPARATE compiler out-of-band (config.mak is saved+restored) so the shared +# armv8m-tcc other agents depend on is never mutated. +# +# Usage: +# scripts/asan_sweep.sh [options] +# +# --corpus C gcc-torture | tests2 | ir_tests | all (default: all) +# --olevels L comma list of opt levels (default: -O0,-O1,-O2) +# --shard i/N sweep only shard i of N (1-based) for parallel runs +# --limit N cap number of files swept (after sharding) +# --timeout S per-compile timeout in seconds (default: 60) +# --compiler PATH compiler to use (default: ./armv8m-tcc; the ASAN build) +# --with-ubsan ALSO build an out-of-band UBSan compiler and sweep with it +# (rebuilds into a temp dir, restoring config.mak; SLOW) +# --report PATH write the deduped report to PATH (also printed) +# --raw-hits PATH append every raw hit line (file|olevel|key) to PATH +# -h | --help show this help +# +# Examples: +# # full sweep, all corpora, all O-levels: +# scripts/asan_sweep.sh --corpus all +# # one shard of gcc-torture for a parallel fleet: +# scripts/asan_sweep.sh --corpus gcc-torture --shard 3/40 +# # quick smoke: +# scripts/asan_sweep.sh --corpus tests2 --limit 30 +# +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +REPO="$(cd "$SCRIPT_DIR/.." && pwd)" +HELPER="$SCRIPT_DIR/asan_sweep.py" + +# ---- defaults ---- +CORPUS="all" +OLEVELS="-O0,-O1,-O2" +SHARD="" +LIMIT="0" +TIMEOUT="60" +COMPILER="$REPO/armv8m-tcc" +WITH_UBSAN="0" +REPORT="" +RAW_HITS="" + +usage() { sed -n '2,45p' "${BASH_SOURCE[0]}" | sed 's/^# \{0,1\}//'; } + +while [[ $# -gt 0 ]]; do + case "$1" in + --corpus) CORPUS="$2"; shift 2;; + --olevels) OLEVELS="$2"; shift 2;; + --shard) SHARD="$2"; shift 2;; + --limit) LIMIT="$2"; shift 2;; + --timeout) TIMEOUT="$2"; shift 2;; + --compiler) COMPILER="$2"; shift 2;; + --with-ubsan) WITH_UBSAN="1"; shift;; + --report) REPORT="$2"; shift 2;; + --raw-hits) RAW_HITS="$2"; shift 2;; + -h|--help) usage; exit 0;; + *) echo "unknown option: $1" >&2; usage; exit 2;; + esac +done + +# -------------------------------------------------------------------------- +# Reconstruct the EXACT include/ABI flags the real torture harness passes when +# CC is armv8m-tcc. Mirrors tests/ir_tests/qemu/mps2-an505/Makefile: +# GCC_ABI_FLAGS = -mcpu=cortex-m33 -mthumb -mfloat-abi=soft +# CFLAGS += -nostdlib -fvisibility=hidden $(GCC_ABI_FLAGS) -ffunction-sections +# (armv8m-tcc branch) -I libc_includes -I libc_imports -I newlib +# -I $(ARM_SYSROOT)/include -I $(TCC_PATH)/include +# -------------------------------------------------------------------------- +GCC_ABI_FLAGS="-mcpu=cortex-m33 -mthumb -mfloat-abi=soft" +ABI_FLAGS="-nostdlib -fvisibility=hidden $GCC_ABI_FLAGS -ffunction-sections" + +LIBC_INCLUDES="$(realpath "$REPO/tests/ir_tests/libc_includes")" +LIBC_IMPORTS="$(realpath "$REPO/tests/ir_tests/libc_imports")" +NEWLIB_INCLUDES="$LIBC_INCLUDES/newlib" +ARM_SYSROOT="$(arm-none-eabi-gcc $GCC_ABI_FLAGS --print-sysroot 2>/dev/null || echo /usr/arm-none-eabi)" +INCLUDE_FLAGS="-I$LIBC_INCLUDES -I$LIBC_IMPORTS -I$NEWLIB_INCLUDES -I$ARM_SYSROOT/include -I$REPO/include" + +run_sweep() { + local compiler="$1" tag="$2" report_arg=() + echo "================================================================" + echo " Sweep ($tag): $compiler" + echo "================================================================" + local report_path="" + if [[ -n "$REPORT" ]]; then + if [[ "$tag" == "ubsan" ]]; then + report_path="${REPORT%.txt}.ubsan.txt" + else + report_path="$REPORT" + fi + report_arg=(--report "$report_path") + fi + local raw_arg=() + [[ -n "$RAW_HITS" ]] && raw_arg=(--list-hits-raw "$RAW_HITS") + local shard_arg=() + [[ -n "$SHARD" ]] && shard_arg=(--shard "$SHARD") + + # Values that begin with '-' (olevels, the -I/-m flag bundles) are passed with + # '=' so argparse does not mistake them for options. + python3 "$HELPER" \ + --compiler "$compiler" \ + --corpus "$CORPUS" \ + --olevels="$OLEVELS" \ + --limit "$LIMIT" \ + --timeout "$TIMEOUT" \ + --include-flags="$INCLUDE_FLAGS" \ + --abi-flags="$ABI_FLAGS" \ + "${shard_arg[@]}" \ + "${report_arg[@]}" \ + "${raw_arg[@]}" +} + +# ---- ASAN sweep (the default, using the existing shared compiler) ---- +if [[ ! -x "$COMPILER" ]]; then + echo "error: compiler not found or not executable: $COMPILER" >&2 + echo " build it with 'make cross' first." >&2 + exit 2 +fi +run_sweep "$COMPILER" "asan" + +# ---- optional out-of-band UBSan sweep ---- +if [[ "$WITH_UBSAN" == "1" ]]; then + echo + echo "################################################################" + echo "# --with-ubsan: building a SEPARATE UBSan compiler out-of-band" + echo "# (config.mak is saved + restored; shared armv8m-tcc untouched)" + echo "################################################################" + + UBSAN_DIR="$(mktemp -d "${TMPDIR:-/tmp}/asan_sweep_ubsan.XXXXXX")" + CONFIG_BAK="$(mktemp "${TMPDIR:-/tmp}/config.mak.bak.XXXXXX")" + cp "$REPO/config.mak" "$CONFIG_BAK" + + restore_config() { + cp "$CONFIG_BAK" "$REPO/config.mak" + rm -f "$CONFIG_BAK" + echo "restored config.mak" + } + trap restore_config EXIT + + UBSAN_TCC="$UBSAN_DIR/armv8m-tcc" + ( + cd "$REPO" + # Reconfigure with UBSan (this rewrites config.mak — restored on exit). + ./configure --enable-ubsan >/dev/null + # Build the cross compiler into the temp dir without clobbering the shared + # armv8m-tcc: build normally, then move the artifact aside and restore the + # shared one from git (it is a tracked binary in this repo layout — if not, + # the ASAN compiler is rebuilt by the next 'make cross' anyway). + make cross >/dev/null 2>&1 || { echo "UBSan build failed" >&2; exit 1; } + cp "$REPO/armv8m-tcc" "$UBSAN_TCC" + ) + # Rebuild the shared ASAN compiler so concurrent agents see it unchanged. + restore_config + trap - EXIT + ( cd "$REPO" && make cross >/dev/null 2>&1 ) || \ + echo "warning: could not rebuild shared ASAN armv8m-tcc; run 'make cross'" >&2 + + run_sweep "$UBSAN_TCC" "ubsan" + rm -rf "$UBSAN_DIR" +fi diff --git a/scripts/diff_olevels.py b/scripts/diff_olevels.py new file mode 100644 index 00000000..0b41c855 --- /dev/null +++ b/scripts/diff_olevels.py @@ -0,0 +1,167 @@ +#!/usr/bin/env python3 +"""Track 2 -- optimization-level self-consistency differential. + +Oracle: a program's observable output (stdout + exit code) must be **identical** +at ``-O0``, ``-O1`` and ``-O2``. Any divergence means an optimization changed +behaviour -> a candidate miscompile, with the offending O-level pinned. + +For each seed we generate a UB-free random C program (``tests/fuzz/gen_c.py``), +compile it with ``armv8m-tcc`` at each O-level, run each under QEMU +``mps2-an505`` (reusing the ``tests/ir_tests`` plumbing via +``tests/fuzz/fuzz_harness.py``), and compare the (stdout, exit) signatures. + +On divergence the offending ``.c`` and the per-level outputs are saved to a +results directory and the seed is reported. Because the generator is UB-free by +construction, a divergence here is a real self-consistency failure (re-check the +generator's guarantees before filing, per the plan's rules). + +Usage: + python scripts/diff_olevels.py --seeds 0-49 + python scripts/diff_olevels.py --seed 0 --seed 7 --seed 42 + python scripts/diff_olevels.py --count 100 --start 0 --results-dir /tmp/fuzz_olevels + python scripts/diff_olevels.py --file path/to/program.c # one fixed file + +Exit code: 0 if all consistent, 1 if any divergence (or harness unusable when +``--require-qemu`` is given). +""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + +# Make tests/fuzz importable. +REPO_ROOT = Path(__file__).resolve().parent.parent +FUZZ_DIR = REPO_ROOT / "tests" / "fuzz" +if str(FUZZ_DIR) not in sys.path: + sys.path.insert(0, str(FUZZ_DIR)) + +import fuzz_harness as H # noqa: E402 +from gen_c import generate_program # noqa: E402 + +DEFAULT_OPT_LEVELS = ["-O0", "-O1", "-O2"] + + +def parse_seed_spec(args) -> list[int]: + """Resolve --seed / --seeds RANGE / --count+--start into a seed list.""" + seeds: list[int] = [] + if args.seeds: + for token in args.seeds.split(","): + token = token.strip() + if "-" in token: + lo, hi = token.split("-", 1) + seeds.extend(range(int(lo), int(hi) + 1)) + elif token: + seeds.append(int(token)) + seeds.extend(args.seed or []) + if args.count: + seeds.extend(range(args.start, args.start + args.count)) + if not seeds and not args.file: + seeds = list(range(0, 20)) # sensible default + # De-dup, preserve order. + seen = set() + out = [] + for s in seeds: + if s not in seen: + seen.add(s) + out.append(s) + return out + + +def _save_divergence(results_dir: Path, tag: str, source: Path, results) -> Path: + results_dir.mkdir(parents=True, exist_ok=True) + case_dir = results_dir / tag + case_dir.mkdir(parents=True, exist_ok=True) + dest_c = case_dir / source.name + dest_c.write_text(Path(source).read_text()) + summary = [f"# O-level self-consistency divergence: {tag}", ""] + for r in results: + summary.append(f"[{r.label}] ok={r.ok} exit={r.exit_code} " + f"stdout={r.stdout.strip()!r} err={r.error.strip()!r}") + (case_dir / "outputs.txt").write_text("\n".join(summary) + "\n") + return case_dir + + +def check_one(source: Path, opt_levels, work_dir: Path): + """Run ``source`` at every opt level; return (consistent, results).""" + results = [H.run_with_tcc(source, o, work_dir) for o in opt_levels] + # A build/run failure is itself a divergence-worthy event to report. + if not all(r.ok for r in results): + return False, results + sigs = {r.signature for r in results} + return (len(sigs) == 1), results + + +def main(argv=None) -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--seed", type=int, action="append", help="a single seed (repeatable)") + ap.add_argument("--seeds", type=str, help="comma list / ranges, e.g. '0-49,100'") + ap.add_argument("--count", type=int, default=0, help="number of seeds from --start") + ap.add_argument("--start", type=int, default=0, help="first seed for --count") + ap.add_argument("--file", type=str, default=None, + help="diff a fixed .c file instead of generated seeds") + ap.add_argument("--opt-levels", type=str, default=",".join(DEFAULT_OPT_LEVELS), + help="comma-separated opt levels (default -O0,-O1,-O2)") + ap.add_argument("--results-dir", type=str, default=None, + help="where to save divergences (default tests/fuzz/results/olevels)") + ap.add_argument("--work-dir", type=str, default=None, + help="scratch build dir (default /_build)") + ap.add_argument("--require-qemu", action="store_true", + help="exit non-zero if QEMU/newlib is unprepared (default: skip)") + args = ap.parse_args(argv) + + usable, reason = H.qemu_available() + if not usable: + msg = f"[diff_olevels] QEMU/newlib not usable: {reason}" + print(msg, file=sys.stderr) + return 1 if args.require_qemu else 0 + + opt_levels = [o.strip() for o in args.opt_levels.split(",") if o.strip()] + results_dir = Path(args.results_dir) if args.results_dir else (FUZZ_DIR / "results" / "olevels") + work_dir = Path(args.work_dir) if args.work_dir else (results_dir / "_build") + work_dir.mkdir(parents=True, exist_ok=True) + + divergences = 0 + checked = 0 + + if args.file: + source = Path(args.file) + consistent, results = check_one(source, opt_levels, work_dir) + checked += 1 + status = "OK " if consistent else "DIVERGE" + sigs = " | ".join(f"{r.label}={r.stdout.strip()!r}/{r.exit_code}" for r in results) + print(f"[{status}] {source.name}: {sigs}") + if not consistent: + divergences += 1 + d = _save_divergence(results_dir, source.stem, source, results) + print(f" saved -> {d}") + else: + seeds = parse_seed_spec(args) + for seed in seeds: + src = work_dir / f"fuzz_{seed}.c" + src.write_text(generate_program(seed)) + consistent, results = check_one(src, opt_levels, work_dir) + checked += 1 + if consistent: + ref = results[0].stdout.strip() + print(f"[OK ] seed {seed}: {ref!r} exit={results[0].exit_code}") + else: + divergences += 1 + sigs = " | ".join( + f"{r.label}={r.stdout.strip()!r}/{r.exit_code}" + f"{'' if r.ok else ' (' + r.error.strip().splitlines()[0] + ')' if r.error.strip() else ''}" + for r in results + ) + print(f"[DIVERGE] seed {seed}: {sigs}") + d = _save_divergence(results_dir, f"seed_{seed}", src, results) + print(f" repro saved -> {d}") + + print(f"\n[diff_olevels] checked={checked} divergences={divergences} " + f"opt_levels={opt_levels}") + return 1 if divergences else 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/scripts/diff_vs_gcc.py b/scripts/diff_vs_gcc.py new file mode 100644 index 00000000..1ae1bfe7 --- /dev/null +++ b/scripts/diff_vs_gcc.py @@ -0,0 +1,254 @@ +#!/usr/bin/env python3 +"""Track 3 -- differential vs arm-none-eabi-gcc. + +Oracle: **gcc** (trusted). The same C program is compiled by ``armv8m-tcc`` +(at each O-level) and by ``arm-none-eabi-gcc -O2``, both run under the SAME QEMU +``mps2-an505`` harness (reused from ``tests/fuzz/fuzz_harness.py``). Any tcc +level whose (stdout, exit) signature differs from gcc's is a candidate +miscompile -- including bugs where all tcc levels AGREE but are wrong, which +Track 2 cannot catch. + +Two modes +--------- +``--mode random`` (default, the priority path) + Generate UB-free random C programs (``tests/fuzz/gen_c.py``) and diff each + tcc O-level against the gcc reference. UB-freedom is guaranteed by the + generator, so a divergence is a real wrong-output bug (re-verify generator + guarantees before filing, per plan rules). + +``--mode torture`` + Run the existing gcc c-torture **execute** tests through tcc. These tests + are self-checking -- they ``abort()`` (non-zero exit) on a wrong result -- + so we treat a non-zero exit as a candidate miscompile, triaged against the + suite's known skip / xfail lists (reused from ``tests/gcctestsuite``). No + gcc run is needed in this mode (the program is its own oracle). + +Usage: + python scripts/diff_vs_gcc.py --seeds 0-49 + python scripts/diff_vs_gcc.py --mode random --count 100 --start 0 + python scripts/diff_vs_gcc.py --file prog.c --gcc-opt -O2 + python scripts/diff_vs_gcc.py --mode torture --limit 200 + +Exit code: 0 if everything matched gcc / passed; 1 on any candidate miscompile +(or harness unusable with --require-qemu). +""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + +REPO_ROOT = Path(__file__).resolve().parent.parent +FUZZ_DIR = REPO_ROOT / "tests" / "fuzz" +if str(FUZZ_DIR) not in sys.path: + sys.path.insert(0, str(FUZZ_DIR)) + +import fuzz_harness as H # noqa: E402 +from gen_c import generate_program # noqa: E402 + +DEFAULT_TCC_OPT_LEVELS = ["-O0", "-O1", "-O2"] + + +# --------------------------------------------------------------------------- +# seed parsing (shared shape with diff_olevels) +# --------------------------------------------------------------------------- + +def parse_seed_spec(args) -> list[int]: + seeds: list[int] = [] + if args.seeds: + for token in args.seeds.split(","): + token = token.strip() + if "-" in token: + lo, hi = token.split("-", 1) + seeds.extend(range(int(lo), int(hi) + 1)) + elif token: + seeds.append(int(token)) + seeds.extend(args.seed or []) + if args.count: + seeds.extend(range(args.start, args.start + args.count)) + if not seeds and not args.file: + seeds = list(range(0, 20)) + seen, out = set(), [] + for s in seeds: + if s not in seen: + seen.add(s) + out.append(s) + return out + + +def _save_divergence(results_dir: Path, tag: str, source: Path, ref, tcc_results) -> Path: + results_dir.mkdir(parents=True, exist_ok=True) + case_dir = results_dir / tag + case_dir.mkdir(parents=True, exist_ok=True) + (case_dir / source.name).write_text(Path(source).read_text()) + lines = [f"# tcc-vs-gcc divergence: {tag}", ""] + lines.append(f"[{ref.label} REFERENCE] ok={ref.ok} exit={ref.exit_code} " + f"stdout={ref.stdout.strip()!r} err={ref.error.strip()!r}") + for r in tcc_results: + agree = "MATCH" if (r.ok and ref.ok and r.signature == ref.signature) else "DIFF" + lines.append(f"[{r.label}] {agree} ok={r.ok} exit={r.exit_code} " + f"stdout={r.stdout.strip()!r} err={r.error.strip()!r}") + (case_dir / "outputs.txt").write_text("\n".join(lines) + "\n") + return case_dir + + +# --------------------------------------------------------------------------- +# Mode: random +# --------------------------------------------------------------------------- + +def run_random(args) -> int: + ok_ref, reason = H.gcc_reference_available() + if not ok_ref: + print(f"[diff_vs_gcc] gcc reference not usable: {reason}", file=sys.stderr) + return 1 if args.require_qemu else 0 + + tcc_opts = [o.strip() for o in args.tcc_opt_levels.split(",") if o.strip()] + gcc_opt = args.gcc_opt + results_dir = Path(args.results_dir) if args.results_dir else (FUZZ_DIR / "results" / "vs_gcc") + work_dir = Path(args.work_dir) if args.work_dir else (results_dir / "_build") + work_dir.mkdir(parents=True, exist_ok=True) + + divergences = 0 + checked = 0 + + def diff_source(source: Path, tag: str): + nonlocal divergences, checked + ref = H.run_with_gcc(source, gcc_opt, work_dir) + checked += 1 + if not ref.ok: + print(f"[GCC-FAIL] {tag}: reference build/run failed: " + f"{ref.error.strip().splitlines()[0] if ref.error.strip() else '?'}") + return + tcc_results = [H.run_with_tcc(source, o, work_dir) for o in tcc_opts] + mismatched = [r for r in tcc_results if not (r.ok and r.signature == ref.signature)] + if not mismatched: + print(f"[OK ] {tag}: gcc{gcc_opt}={ref.stdout.strip()!r}/{ref.exit_code} " + f"(all tcc levels match)") + return + divergences += 1 + parts = [f"gcc{gcc_opt}={ref.stdout.strip()!r}/{ref.exit_code}"] + for r in tcc_results: + mark = "" if (r.ok and r.signature == ref.signature) else " <-- DIFF" + parts.append(f"{r.label}={r.stdout.strip()!r}/{r.exit_code}{mark}") + print(f"[DIVERGE] {tag}:\n " + "\n ".join(parts)) + d = _save_divergence(results_dir, tag.replace(" ", "_"), source, ref, tcc_results) + print(f" repro saved -> {d}") + + if args.file: + diff_source(Path(args.file), Path(args.file).stem) + else: + for seed in parse_seed_spec(args): + src = work_dir / f"fuzz_{seed}.c" + src.write_text(generate_program(seed)) + diff_source(src, f"seed_{seed}") + + print(f"\n[diff_vs_gcc:random] checked={checked} divergences={divergences} " + f"tcc_opts={tcc_opts} gcc_opt={gcc_opt}") + return 1 if divergences else 0 + + +# --------------------------------------------------------------------------- +# Mode: torture (self-checking gcc execute tests through tcc) +# --------------------------------------------------------------------------- + +def run_torture(args) -> int: + usable, reason = H.qemu_available() + if not usable: + print(f"[diff_vs_gcc] QEMU/newlib not usable: {reason}", file=sys.stderr) + return 1 if args.require_qemu else 0 + + # Reuse the gcctestsuite discovery + skip/xfail lists. + import importlib.util + gcc_conf_path = REPO_ROOT / "tests" / "gcctestsuite" / "conftest.py" + spec = importlib.util.spec_from_file_location("gcc_conftest", gcc_conf_path) + gcc_conf = importlib.util.module_from_spec(spec) + spec.loader.exec_module(gcc_conf) + + if not gcc_conf.GCC_TORTURE_PATH.exists(): + print(f"[diff_vs_gcc:torture] torture tests not found at " + f"{gcc_conf.GCC_TORTURE_PATH}; run 'make download-gcc-tests'", + file=sys.stderr) + return 1 if args.require_qemu else 0 + + tcc_opts = [o.strip() for o in args.tcc_opt_levels.split(",") if o.strip()] + results_dir = Path(args.results_dir) if args.results_dir else (FUZZ_DIR / "results" / "torture") + work_dir = Path(args.work_dir) if args.work_dir else (results_dir / "_build") + work_dir.mkdir(parents=True, exist_ok=True) + + cases = gcc_conf.discover_gcc_execute_tests() + if args.limit: + cases = cases[: args.limit] + + candidates = 0 + ran = 0 + skipped = 0 + + for tc in cases: + skip = gcc_conf.should_skip_gcc_test(tc.source) + xfail = gcc_conf.is_xfail_test(tc.source) + if skip or xfail: + skipped += 1 + continue + for opt in tcc_opts: + cflags = opt + if tc.dg_options: + cflags = f"{opt} {tc.dg_options}" + # Reuse the tcc QEMU path; the program self-checks via abort(). + res = H.run_with_tcc(tc.source, cflags, work_dir) + ran += 1 + # A self-checking execute test passes iff it exits 0. + passed = res.ok and res.exit_code == 0 + if passed: + continue + candidates += 1 + reason = (res.error.strip().splitlines()[0] + if res.error.strip() else f"exit={res.exit_code}") + print(f"[CANDIDATE] {tc.source.stem} {opt}: {reason}") + results_dir.mkdir(parents=True, exist_ok=True) + log = results_dir / f"{tc.source.stem}{opt.replace('-', '')}.txt" + log.write_text( + f"# torture candidate miscompile: {tc.source} {opt}\n" + f"exit={res.exit_code} ok={res.ok}\n" + f"stdout={res.stdout.strip()!r}\n" + f"error={res.error.strip()!r}\n" + ) + + print(f"\n[diff_vs_gcc:torture] ran={ran} candidates={candidates} " + f"skipped(known)={skipped} tcc_opts={tcc_opts}") + return 1 if candidates else 0 + + +# --------------------------------------------------------------------------- + +def main(argv=None) -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--mode", choices=["random", "torture"], default="random", + help="random C generator (default) or gcc-torture execute tests") + # random-mode inputs + ap.add_argument("--seed", type=int, action="append", help="single seed (repeatable)") + ap.add_argument("--seeds", type=str, help="comma list / ranges, e.g. '0-49,100'") + ap.add_argument("--count", type=int, default=0, help="number of seeds from --start") + ap.add_argument("--start", type=int, default=0, help="first seed for --count") + ap.add_argument("--file", type=str, default=None, help="diff a fixed .c file") + ap.add_argument("--gcc-opt", type=str, default="-O2", help="gcc reference O-level") + ap.add_argument("--tcc-opt-levels", type=str, default=",".join(DEFAULT_TCC_OPT_LEVELS), + help="comma-separated tcc opt levels") + # torture-mode inputs + ap.add_argument("--limit", type=int, default=0, + help="(torture) cap the number of discovered tests") + # shared + ap.add_argument("--results-dir", type=str, default=None) + ap.add_argument("--work-dir", type=str, default=None) + ap.add_argument("--require-qemu", action="store_true", + help="exit non-zero if QEMU/newlib is unprepared (default: skip)") + args = ap.parse_args(argv) + + if args.mode == "torture": + return run_torture(args) + return run_random(args) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/scripts/reduce_divergence.py b/scripts/reduce_divergence.py new file mode 100644 index 00000000..46fd1a1a --- /dev/null +++ b/scripts/reduce_divergence.py @@ -0,0 +1,131 @@ +#!/usr/bin/env python3 +"""Delta-reduce a divergent C program to a smaller repro (Phase BH helper). + +Given a ``.c`` file that produces different output under armv8m-tcc at two +different optimization levels (the "interestingness" property), greedily delete +top-level functions and individual statement lines while the divergence persists, +yielding a smaller program with the same bug. Reuses the QEMU harness +(``tests/fuzz/fuzz_harness.py``) so the reduced program is still validated +end-to-end on the real target. + +This is intentionally simple (line/function granularity, not a full C reducer +like creduce) -- enough to hand a much smaller repro to bug-fix work. + +Usage: + python scripts/reduce_divergence.py FILE.c --low -O0 --high -O1 -o reduced.c + python scripts/reduce_divergence.py FILE.c --low -O0 --high -O2 + +The reduced program is only guaranteed to *reproduce the divergence*; it is not +re-checked for UB (the original was UB-free; deletions cannot introduce signed +overflow etc. given the generator's all-unsigned discipline, but treat the +reduced output as a starting point for manual minimization). +""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + +REPO_ROOT = Path(__file__).resolve().parent.parent +FUZZ_DIR = REPO_ROOT / "tests" / "fuzz" +if str(FUZZ_DIR) not in sys.path: + sys.path.insert(0, str(FUZZ_DIR)) + +import fuzz_harness as H # noqa: E402 + + +def diverges(source_text: str, low: str, high: str, work_dir: Path) -> bool: + """True iff tcc at ``low`` and ``high`` produce different (stdout, exit) AND + both builds/runs succeed (so we don't 'reduce' into a compile error).""" + tmp = work_dir / "candidate.c" + tmp.write_text(source_text) + rl = H.run_with_tcc(tmp, low, work_dir) + rh = H.run_with_tcc(tmp, high, work_dir) + if not (rl.ok and rh.ok): + return False + return rl.signature != rh.signature + + +def _split_top_level(text: str) -> list[str]: + """Return lines; we operate at line granularity but never remove the + csmix/printf scaffolding that defines the observable output.""" + return text.splitlines(keepends=False) + + +def reduce_text(text: str, low: str, high: str, work_dir: Path) -> str: + work_dir.mkdir(parents=True, exist_ok=True) + assert diverges(text, low, high, work_dir), "input does not diverge" + + lines = _split_top_level(text) + # Protect lines that are structurally required to keep a compilable program + # that still prints something: includes, csmix, the main signature, the + # printf/return, and brace-only lines (cheap structural safety). + def protected(ln: str) -> bool: + s = ln.strip() + return ( + s.startswith("#include") + or "csmix" in s + or s.startswith("int main") + or s.startswith("printf") + or s.startswith("return") + or s in ("{", "}") + or s.startswith("struct S") + or s.startswith("unsigned cs =") + ) + + changed = True + while changed: + changed = False + i = 0 + while i < len(lines): + if protected(lines[i]): + i += 1 + continue + trial = lines[:i] + lines[i + 1:] + if diverges("\n".join(trial) + "\n", low, high, work_dir): + lines = trial + changed = True + # don't advance i; the next line shifted into position i + else: + i += 1 + return "\n".join(lines) + "\n" + + +def main(argv=None) -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("file", help="divergent .c file to reduce") + ap.add_argument("--low", default="-O0", help="reference O-level (default -O0)") + ap.add_argument("--high", default="-O2", help="divergent O-level (default -O2)") + ap.add_argument("-o", "--output", default=None, help="write reduced program here") + ap.add_argument("--work-dir", default=None, help="scratch build dir") + args = ap.parse_args(argv) + + usable, reason = H.qemu_available() + if not usable: + print(f"[reduce] QEMU/newlib not usable: {reason}", file=sys.stderr) + return 2 + + src = Path(args.file) + text = src.read_text() + work_dir = Path(args.work_dir) if args.work_dir else (FUZZ_DIR / "results" / "_reduce") + work_dir.mkdir(parents=True, exist_ok=True) + + if not diverges(text, args.low, args.high, work_dir): + print(f"[reduce] {src} does not diverge at {args.low} vs {args.high}; nothing to do", + file=sys.stderr) + return 1 + + before = len(text.splitlines()) + reduced = reduce_text(text, args.low, args.high, work_dir) + after = len(reduced.splitlines()) + out = Path(args.output) if args.output else src.with_name(src.stem + "_reduced.c") + out.write_text(reduced) + print(f"[reduce] {src.name}: {before} -> {after} lines " + f"(still diverges {args.low} vs {args.high}) -> {out}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tccgen.c b/tccgen.c index 178df89e..2747788b 100644 --- a/tccgen.c +++ b/tccgen.c @@ -67,6 +67,56 @@ static int local_scope; static int func_param_decl_depth; ST_DATA char debug_modes; +typedef struct FuncallScratch +{ + SValue *saved_args; + unsigned char **saved_args_cid; + int *saved_args_cid_size; + int saved_arg_count; + struct FuncallScratch *next; +} FuncallScratch; + +static FuncallScratch *funcall_scratch_stack; + +static void funcall_scratch_free(FuncallScratch *fs) +{ + int i; + + if (!fs) + return; + tcc_free(fs->saved_args); + for (i = 0; i < fs->saved_arg_count; i++) + tcc_free(fs->saved_args_cid[i]); + tcc_free(fs->saved_args_cid); + tcc_free(fs->saved_args_cid_size); + tcc_free(fs); +} + +static void funcall_scratch_pop_free(FuncallScratch *fs) +{ + FuncallScratch **p; + + for (p = &funcall_scratch_stack; *p; p = &(*p)->next) + { + if (*p == fs) + { + *p = fs->next; + break; + } + } + funcall_scratch_free(fs); +} + +static void funcall_scratch_free_all(void) +{ + while (funcall_scratch_stack) + { + FuncallScratch *next = funcall_scratch_stack->next; + funcall_scratch_free(funcall_scratch_stack); + funcall_scratch_stack = next; + } +} + typedef struct PendingAliasDef { Sym *alias_sym; @@ -1084,6 +1134,7 @@ ST_FUNC void tccgen_finish(TCCState *s1) tcc_ir_func_write_summary_clear_all(); /* Same for the TU-wide read/call summary used by dead-static-store elim. */ tcc_ir_tu_func_summary_clear_all(); + funcall_scratch_free_all(); tcc_free(pending_aliases); pending_aliases = NULL; @@ -1631,6 +1682,11 @@ ST_FUNC void sym_pop(Sym **ptop, Sym *b, int keep) ps = &ts->sym_identifier; *ps = s->prev_tok; } + if (!keep && s->const_init_data) + { + tcc_free(s->const_init_data); + s->const_init_data = NULL; + } /* Don't free symbols that have been exported to ELF (sym->c != 0) as they may still be referenced by IR instructions */ if (!keep && s->c == 0) @@ -15722,9 +15778,15 @@ static void unary_funcall(void) if (pc > saved_args_cap) saved_args_cap = pc; } - SValue *saved_args = tcc_mallocz(saved_args_cap * sizeof(SValue)); - unsigned char **saved_args_cid = tcc_mallocz(saved_args_cap * sizeof(unsigned char *)); - int *saved_args_cid_size = tcc_mallocz(saved_args_cap * sizeof(int)); + FuncallScratch *saved_scratch = tcc_mallocz(sizeof(*saved_scratch)); + saved_scratch->saved_args = tcc_mallocz(saved_args_cap * sizeof(SValue)); + saved_scratch->saved_args_cid = tcc_mallocz(saved_args_cap * sizeof(unsigned char *)); + saved_scratch->saved_args_cid_size = tcc_mallocz(saved_args_cap * sizeof(int)); + saved_scratch->next = funcall_scratch_stack; + funcall_scratch_stack = saved_scratch; + SValue *saved_args = saved_scratch->saved_args; + unsigned char **saved_args_cid = saved_scratch->saved_args_cid; + int *saved_args_cid_size = saved_scratch->saved_args_cid_size; int saved_arg_count = 0; int can_try_fold = 0; int can_inline_builtin = 0; @@ -16194,6 +16256,7 @@ static void unary_funcall(void) aapcs_last_const_init = NULL; } saved_arg_count++; + saved_scratch->saved_arg_count = saved_arg_count; } else { @@ -16312,7 +16375,10 @@ static void unary_funcall(void) { saved_args[nb_args - 1 - n] = *vtop; if (n == 0) + { saved_arg_count = nb_args; + saved_scratch->saved_arg_count = saved_arg_count; + } } /* We evaluate right-to-left; assign 0-based parameter indices @@ -17506,11 +17572,8 @@ static void unary_funcall(void) } } } /* end of else block for non-folded function calls */ - tcc_free(saved_args); - for (int ci = 0; ci < saved_arg_count; ci++) - tcc_free(saved_args_cid[ci]); - tcc_free(saved_args_cid); - tcc_free(saved_args_cid_size); + saved_scratch->saved_arg_count = saved_arg_count; + funcall_scratch_pop_free(saved_scratch); if (s->f.func_noreturn) { if (debug_modes) @@ -28038,7 +28101,7 @@ static void decl_initializer_alloc(CType *type, AttributeDef *ad, int r, int has /* restore parse state if needed */ if (init_str) { - end_macro(); + end_macro_to(init_str); next(); } @@ -29019,41 +29082,14 @@ static void gen_instrument_call(Sym *cur_func_sym, const char *hook_name) } #ifdef CONFIG_TCC_DEBUG -/* Returns 1 if `pass_name` matches the comma-separated list in - * s->dump_ir_passes (or the list contains the special token "all"). - * Used by DUMP_AFTER_PASS to gate per-pass IR dumps. */ -static int dump_ir_passes_match(TCCState *s, const char *pass_name) -{ - if (!s->dump_ir_passes || !pass_name) - return 0; - const char *p = s->dump_ir_passes; - size_t name_len = strlen(pass_name); - while (*p) - { - const char *comma = strchr(p, ','); - size_t tok_len = comma ? (size_t)(comma - p) : strlen(p); - if (tok_len == 3 && !memcmp(p, "all", 3)) - return 1; - if (tok_len == name_len && !memcmp(p, pass_name, name_len)) - return 1; - if (!comma) - break; - p = comma + 1; - } - return 0; -} - /* If pass_name matches -dump-ir-passes selection, dump the IR labeled with * the pass name. Intended to be called immediately after a - * tcc_ir_opt_() call to bisect which pass corrupts the IR. */ + * tcc_ir_opt_() call to bisect which pass corrupts the IR. Thin wrapper + * over the shared implementation in ir/dump.c (also used by the SSA driver). */ static void dump_ir_after_pass(TCCState *s, TCCIRState *ir, const char *pass_name) { - if (!dump_ir_passes_match(s, pass_name)) - return; - tcc_ir_dump_set_show_physical_regs(0); - printf("=== AFTER %s ===\n", pass_name); - tcc_ir_show(ir); - printf("=== END AFTER %s ===\n", pass_name); + (void)s; + tcc_ir_dump_after_pass(ir, pass_name); } /* Run a pass call and dump if selected. `expr` is the call, `name` is a diff --git a/tccir.h b/tccir.h index 36d8bb15..aa9a5b86 100644 --- a/tccir.h +++ b/tccir.h @@ -620,6 +620,16 @@ typedef struct TCCIRState * Entry = lsb (bits 0-7) | (width << 8); width >= 1 so a real BFI entry is * never 0. Consumed by tcc_gen_machine_bfi_mop. */ uint16_t *bfi_params; + + /* Codegen temporaries owned by tcc_ir_codegen_generate while it is running. + * They are normally freed before return; tcc_ir_free also releases them when + * a compile error longjmps out of codegen. */ + int *codegen_return_jump_addrs; + int *codegen_dry_insn_scratch; + uint16_t *codegen_dry_insn_saves; + void *codegen_mop_cache; + uint32_t *codegen_cbz_dry_mapping; + uint8_t *codegen_branch_target_reset; } TCCIRState; TCCIRState *tcc_ir_allocate_block(); @@ -659,6 +669,10 @@ void tcc_ir_assign_physical_register(TCCIRState *ir, int vreg, int offset, int r const char *tcc_ir_get_op_name(TccIrOp op); void tcc_ir_show(TCCIRState *ir); void tcc_ir_dump_set_show_physical_regs(int show); +/* -dump-ir-passes= helpers (shared by the legacy optimize loop in tccgen.c and + * the SSA optimizer driver in ir/opt/ssa_opt.c). */ +int tcc_ir_dump_passes_match(TCCState *s, const char *pass_name); +void tcc_ir_dump_after_pass(TCCIRState *ir, const char *pass_name); void tcc_ir_set_addrtaken(TCCIRState *ir, int vreg); IRLiveInterval *tcc_ir_get_live_interval(TCCIRState *ir, int vreg); diff --git a/tests/Makefile b/tests/Makefile index bd45befd..9c5205ad 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -21,6 +21,7 @@ TESTS = \ llong_test-run \ tests2-dir \ pp-dir \ + frontend-dir \ memtest \ dlltest \ cross-test @@ -373,4 +374,5 @@ clean: rm -f ex? tcc_g weaktest.*.txt *.def *.pdb *.obj libtcc_test_mt @$(MAKE) -C tests2 $@ @$(MAKE) -C pp $@ + @$(MAKE) -C frontend $@ diff --git a/tests/frontend/Makefile b/tests/frontend/Makefile new file mode 100644 index 00000000..f323c8bb --- /dev/null +++ b/tests/frontend/Makefile @@ -0,0 +1,28 @@ +# Frontend coverage tests for ARMv8-M TinyCC. +# +# Mirrors tests/pp/Makefile but drives the pytest harness instead of raw +# preprocessor invocations. + +TOP = ../.. +TCC = $(TOP)/bin/armv8m-tcc +PYTHON = python3 + +.PHONY: all test update pp types diagnostics clean + +all test: + $(PYTHON) -m pytest $(CURDIR) -q + +pp: + $(PYTHON) -m pytest $(CURDIR)/test_frontend.py -q -m frontend_pp + +types: + $(PYTHON) -m pytest $(CURDIR)/test_frontend.py -q -m frontend_types + +diagnostics: + $(PYTHON) -m pytest $(CURDIR)/test_frontend.py -q -m frontend_diagnostics + +update: + $(PYTHON) -m pytest $(CURDIR) --update -q + +clean: + find $(CURDIR) -name '*.o' -delete diff --git a/tests/frontend/conftest.py b/tests/frontend/conftest.py new file mode 100644 index 00000000..32f01441 --- /dev/null +++ b/tests/frontend/conftest.py @@ -0,0 +1,57 @@ +"""Shared pytest configuration for the frontend coverage layer.""" + +from pathlib import Path + +import pytest + + +def pytest_addoption(parser): + parser.addoption( + "--update", + action="store_true", + default=False, + help="Regenerate golden files from current compiler output", + ) + parser.addoption( + "--compiler", + action="store", + default=None, + help="Path to the armv8m-tcc cross compiler", + ) + + +def _find_compiler(compiler_override=None): + """Resolve the cross compiler using the requested fallback chain.""" + if compiler_override is not None: + p = Path(compiler_override) + if not p.exists(): + raise FileNotFoundError(f"--compiler not found: {p}") + return p + + tinycc = Path(__file__).parent.parent.parent + candidates = [ + tinycc / "bin" / "armv8m-tcc", + tinycc / "armv8m-tcc", + ] + for cand in candidates: + if cand.exists(): + return cand + raise FileNotFoundError( + "No armv8m-tcc cross compiler found. " + "Build one with `make cross` in libs/tinycc, or pass --compiler." + ) + + +def pytest_configure(config): + """Register custom markers used by the frontend test layers.""" + config.addinivalue_line("markers", "frontend: frontend coverage test") + config.addinivalue_line("markers", "frontend_pp: preprocessor/lexer test") + config.addinivalue_line("markers", "frontend_types: type-system / semantic test") + config.addinivalue_line( + "markers", "frontend_diagnostics: expected-error diagnostic test" + ) + + +@pytest.fixture(scope="session") +def frontend_compiler(pytestconfig): + return _find_compiler(pytestconfig.getoption("compiler")) diff --git a/tests/frontend/diagnostics/01_undeclared.c b/tests/frontend/diagnostics/01_undeclared.c new file mode 100644 index 00000000..aaee6fea --- /dev/null +++ b/tests/frontend/diagnostics/01_undeclared.c @@ -0,0 +1 @@ +int f(void) { return undeclared_var; } diff --git a/tests/frontend/diagnostics/01_undeclared.stderr b/tests/frontend/diagnostics/01_undeclared.stderr new file mode 100644 index 00000000..966b6de7 --- /dev/null +++ b/tests/frontend/diagnostics/01_undeclared.stderr @@ -0,0 +1,2 @@ +error: +'undeclared_var' undeclared diff --git a/tests/frontend/diagnostics/02_redefinition.c b/tests/frontend/diagnostics/02_redefinition.c new file mode 100644 index 00000000..0a2205b0 --- /dev/null +++ b/tests/frontend/diagnostics/02_redefinition.c @@ -0,0 +1,2 @@ +int x = 1; +int x = 2; diff --git a/tests/frontend/diagnostics/02_redefinition.stderr b/tests/frontend/diagnostics/02_redefinition.stderr new file mode 100644 index 00000000..a9d7d640 --- /dev/null +++ b/tests/frontend/diagnostics/02_redefinition.stderr @@ -0,0 +1,2 @@ +error: +redefinition of 'x' diff --git a/tests/frontend/diagnostics/02_type_mismatch.c b/tests/frontend/diagnostics/02_type_mismatch.c new file mode 100644 index 00000000..589e5ea9 --- /dev/null +++ b/tests/frontend/diagnostics/02_type_mismatch.c @@ -0,0 +1 @@ +int f(void) { int x; x = "hello"; return 0; } diff --git a/tests/frontend/diagnostics/02_type_mismatch.stderr b/tests/frontend/diagnostics/02_type_mismatch.stderr new file mode 100644 index 00000000..83ffd6a8 --- /dev/null +++ b/tests/frontend/diagnostics/02_type_mismatch.stderr @@ -0,0 +1,2 @@ +error: +assignment makes integer from pointer diff --git a/tests/frontend/diagnostics/03_incompatible_types.c b/tests/frontend/diagnostics/03_incompatible_types.c new file mode 100644 index 00000000..0d85efde --- /dev/null +++ b/tests/frontend/diagnostics/03_incompatible_types.c @@ -0,0 +1,3 @@ +int f(int x) { + return x + "hello"; +} diff --git a/tests/frontend/diagnostics/03_incompatible_types.stderr b/tests/frontend/diagnostics/03_incompatible_types.stderr new file mode 100644 index 00000000..83ffd6a8 --- /dev/null +++ b/tests/frontend/diagnostics/03_incompatible_types.stderr @@ -0,0 +1,2 @@ +error: +assignment makes integer from pointer diff --git a/tests/frontend/diagnostics/03_redefinition.c b/tests/frontend/diagnostics/03_redefinition.c new file mode 100644 index 00000000..c1146dba --- /dev/null +++ b/tests/frontend/diagnostics/03_redefinition.c @@ -0,0 +1,5 @@ +int f(void) { + int x; + int x; + return 0; +} diff --git a/tests/frontend/diagnostics/03_redefinition.stderr b/tests/frontend/diagnostics/03_redefinition.stderr new file mode 100644 index 00000000..85426ce3 --- /dev/null +++ b/tests/frontend/diagnostics/03_redefinition.stderr @@ -0,0 +1,2 @@ +error: +redeclaration of 'x' diff --git a/tests/frontend/diagnostics/04_invalid_lvalue.c b/tests/frontend/diagnostics/04_invalid_lvalue.c new file mode 100644 index 00000000..de772e38 --- /dev/null +++ b/tests/frontend/diagnostics/04_invalid_lvalue.c @@ -0,0 +1 @@ +int f(void) { int a[2]; a = 0; return 0; } diff --git a/tests/frontend/diagnostics/04_invalid_lvalue.stderr b/tests/frontend/diagnostics/04_invalid_lvalue.stderr new file mode 100644 index 00000000..ad755c64 --- /dev/null +++ b/tests/frontend/diagnostics/04_invalid_lvalue.stderr @@ -0,0 +1,2 @@ +error: +lvalue expected diff --git a/tests/frontend/diagnostics/05_incompatible_call.c b/tests/frontend/diagnostics/05_incompatible_call.c new file mode 100644 index 00000000..8024552f --- /dev/null +++ b/tests/frontend/diagnostics/05_incompatible_call.c @@ -0,0 +1,2 @@ +void g(int x); +void h(void) { g("hello"); } diff --git a/tests/frontend/diagnostics/05_incompatible_call.stderr b/tests/frontend/diagnostics/05_incompatible_call.stderr new file mode 100644 index 00000000..83ffd6a8 --- /dev/null +++ b/tests/frontend/diagnostics/05_incompatible_call.stderr @@ -0,0 +1,2 @@ +error: +assignment makes integer from pointer diff --git a/tests/frontend/diagnostics/break_outside_loop.c b/tests/frontend/diagnostics/break_outside_loop.c new file mode 100644 index 00000000..3fd466ab --- /dev/null +++ b/tests/frontend/diagnostics/break_outside_loop.c @@ -0,0 +1,4 @@ +int f(void) { + break; + return 0; +} diff --git a/tests/frontend/diagnostics/break_outside_loop.stderr b/tests/frontend/diagnostics/break_outside_loop.stderr new file mode 100644 index 00000000..cf48f319 --- /dev/null +++ b/tests/frontend/diagnostics/break_outside_loop.stderr @@ -0,0 +1,2 @@ +error: +cannot break diff --git a/tests/frontend/diagnostics/continue_outside_loop.c b/tests/frontend/diagnostics/continue_outside_loop.c new file mode 100644 index 00000000..3679f912 --- /dev/null +++ b/tests/frontend/diagnostics/continue_outside_loop.c @@ -0,0 +1,4 @@ +int f(void) { + continue; + return 0; +} diff --git a/tests/frontend/diagnostics/continue_outside_loop.stderr b/tests/frontend/diagnostics/continue_outside_loop.stderr new file mode 100644 index 00000000..24664c55 --- /dev/null +++ b/tests/frontend/diagnostics/continue_outside_loop.stderr @@ -0,0 +1,2 @@ +error: +cannot continue diff --git a/tests/frontend/diagnostics/duplicate_label.c b/tests/frontend/diagnostics/duplicate_label.c new file mode 100644 index 00000000..9b9ac577 --- /dev/null +++ b/tests/frontend/diagnostics/duplicate_label.c @@ -0,0 +1,6 @@ +int f(void) { +label: + ; +label: + return 0; +} diff --git a/tests/frontend/diagnostics/duplicate_label.stderr b/tests/frontend/diagnostics/duplicate_label.stderr new file mode 100644 index 00000000..203b3203 --- /dev/null +++ b/tests/frontend/diagnostics/duplicate_label.stderr @@ -0,0 +1,2 @@ +error: +duplicate label diff --git a/tests/frontend/diagnostics/invalid_lvalue.c b/tests/frontend/diagnostics/invalid_lvalue.c new file mode 100644 index 00000000..6ce4bf0c --- /dev/null +++ b/tests/frontend/diagnostics/invalid_lvalue.c @@ -0,0 +1,5 @@ +int f(void) { + int x; + x + 1 = 2; + return 0; +} diff --git a/tests/frontend/diagnostics/invalid_lvalue.stderr b/tests/frontend/diagnostics/invalid_lvalue.stderr new file mode 100644 index 00000000..ad755c64 --- /dev/null +++ b/tests/frontend/diagnostics/invalid_lvalue.stderr @@ -0,0 +1,2 @@ +error: +lvalue expected diff --git a/tests/frontend/diagnostics/missing_closing_brace.c b/tests/frontend/diagnostics/missing_closing_brace.c new file mode 100644 index 00000000..743b8ae7 --- /dev/null +++ b/tests/frontend/diagnostics/missing_closing_brace.c @@ -0,0 +1 @@ +int f(void) { diff --git a/tests/frontend/diagnostics/missing_closing_brace.stderr b/tests/frontend/diagnostics/missing_closing_brace.stderr new file mode 100644 index 00000000..c8a30790 --- /dev/null +++ b/tests/frontend/diagnostics/missing_closing_brace.stderr @@ -0,0 +1,2 @@ +error: +expression expected before diff --git a/tests/frontend/diagnostics/missing_semicolon.c b/tests/frontend/diagnostics/missing_semicolon.c new file mode 100644 index 00000000..4a3e45e7 --- /dev/null +++ b/tests/frontend/diagnostics/missing_semicolon.c @@ -0,0 +1 @@ +int x diff --git a/tests/frontend/diagnostics/missing_semicolon.stderr b/tests/frontend/diagnostics/missing_semicolon.stderr new file mode 100644 index 00000000..e4a402d6 --- /dev/null +++ b/tests/frontend/diagnostics/missing_semicolon.stderr @@ -0,0 +1,2 @@ +error: +';' expected diff --git a/tests/frontend/diagnostics/type_mismatch.c b/tests/frontend/diagnostics/type_mismatch.c new file mode 100644 index 00000000..44c85d64 --- /dev/null +++ b/tests/frontend/diagnostics/type_mismatch.c @@ -0,0 +1,5 @@ +int f(void) { + int x; + x = &x; + return 0; +} diff --git a/tests/frontend/diagnostics/type_mismatch.stderr b/tests/frontend/diagnostics/type_mismatch.stderr new file mode 100644 index 00000000..83ffd6a8 --- /dev/null +++ b/tests/frontend/diagnostics/type_mismatch.stderr @@ -0,0 +1,2 @@ +error: +assignment makes integer from pointer diff --git a/tests/frontend/diagnostics/undeclared_identifier.c b/tests/frontend/diagnostics/undeclared_identifier.c new file mode 100644 index 00000000..0fad89e7 --- /dev/null +++ b/tests/frontend/diagnostics/undeclared_identifier.c @@ -0,0 +1,3 @@ +int f(void) { + return x; +} diff --git a/tests/frontend/diagnostics/undeclared_identifier.stderr b/tests/frontend/diagnostics/undeclared_identifier.stderr new file mode 100644 index 00000000..252ae7ed --- /dev/null +++ b/tests/frontend/diagnostics/undeclared_identifier.stderr @@ -0,0 +1,2 @@ +error: +'x' undeclared diff --git a/tests/frontend/diagnostics/void_variable.c b/tests/frontend/diagnostics/void_variable.c new file mode 100644 index 00000000..35a53e9c --- /dev/null +++ b/tests/frontend/diagnostics/void_variable.c @@ -0,0 +1 @@ +void v; diff --git a/tests/frontend/diagnostics/void_variable.stderr b/tests/frontend/diagnostics/void_variable.stderr new file mode 100644 index 00000000..14b45024 --- /dev/null +++ b/tests/frontend/diagnostics/void_variable.stderr @@ -0,0 +1,2 @@ +error: +declaration of void object diff --git a/tests/frontend/pp/01_macro_expand.c b/tests/frontend/pp/01_macro_expand.c new file mode 100644 index 00000000..cc77180d --- /dev/null +++ b/tests/frontend/pp/01_macro_expand.c @@ -0,0 +1,2 @@ +#define VALUE 42 +int x = VALUE; diff --git a/tests/frontend/pp/01_macro_expand.expect b/tests/frontend/pp/01_macro_expand.expect new file mode 100644 index 00000000..642ca52e --- /dev/null +++ b/tests/frontend/pp/01_macro_expand.expect @@ -0,0 +1 @@ +int x = 42; diff --git a/tests/frontend/pp/01_simple_macro.c b/tests/frontend/pp/01_simple_macro.c new file mode 100644 index 00000000..08753e6b --- /dev/null +++ b/tests/frontend/pp/01_simple_macro.c @@ -0,0 +1,2 @@ +#define ADD(a, b) (a + b) +int x = ADD(1, 2); diff --git a/tests/frontend/pp/01_simple_macro.expect b/tests/frontend/pp/01_simple_macro.expect new file mode 100644 index 00000000..97ccef91 --- /dev/null +++ b/tests/frontend/pp/01_simple_macro.expect @@ -0,0 +1 @@ +int x = (1 + 2); diff --git a/tests/frontend/pp/02_stringify.c b/tests/frontend/pp/02_stringify.c new file mode 100644 index 00000000..9839ca85 --- /dev/null +++ b/tests/frontend/pp/02_stringify.c @@ -0,0 +1,2 @@ +#define STR(x) #x +char *s = STR(hello); diff --git a/tests/frontend/pp/02_stringify.expect b/tests/frontend/pp/02_stringify.expect new file mode 100644 index 00000000..c23d8a24 --- /dev/null +++ b/tests/frontend/pp/02_stringify.expect @@ -0,0 +1 @@ +char *s = "hello"; diff --git a/tests/frontend/pp/03_token_paste.c b/tests/frontend/pp/03_token_paste.c new file mode 100644 index 00000000..2ae43a5b --- /dev/null +++ b/tests/frontend/pp/03_token_paste.c @@ -0,0 +1,2 @@ +#define CAT(a, b) a ## b +int xy = CAT(x, y); diff --git a/tests/frontend/pp/03_token_paste.expect b/tests/frontend/pp/03_token_paste.expect new file mode 100644 index 00000000..6b09dfd4 --- /dev/null +++ b/tests/frontend/pp/03_token_paste.expect @@ -0,0 +1 @@ +int xy = xy; diff --git a/tests/frontend/pp/04_if_expr.c b/tests/frontend/pp/04_if_expr.c new file mode 100644 index 00000000..ea4090e7 --- /dev/null +++ b/tests/frontend/pp/04_if_expr.c @@ -0,0 +1,5 @@ +#if 1 + 1 == 2 +int yes; +#else +int no; +#endif diff --git a/tests/frontend/pp/04_if_expr.expect b/tests/frontend/pp/04_if_expr.expect new file mode 100644 index 00000000..2ab8b3ff --- /dev/null +++ b/tests/frontend/pp/04_if_expr.expect @@ -0,0 +1 @@ +int yes; diff --git a/tests/frontend/pp/04_variadic.c b/tests/frontend/pp/04_variadic.c new file mode 100644 index 00000000..a79094d3 --- /dev/null +++ b/tests/frontend/pp/04_variadic.c @@ -0,0 +1,2 @@ +#define LOG(fmt, ...) printf(fmt, __VA_ARGS__) +LOG("value: %d", 42); diff --git a/tests/frontend/pp/04_variadic.expect b/tests/frontend/pp/04_variadic.expect new file mode 100644 index 00000000..bdf21fbc --- /dev/null +++ b/tests/frontend/pp/04_variadic.expect @@ -0,0 +1 @@ +printf("value: %d", 42); diff --git a/tests/frontend/pp/05_ifdef.c b/tests/frontend/pp/05_ifdef.c new file mode 100644 index 00000000..90757674 --- /dev/null +++ b/tests/frontend/pp/05_ifdef.c @@ -0,0 +1,6 @@ +#define FLAG +#ifdef FLAG +int enabled = 1; +#else +int enabled = 0; +#endif diff --git a/tests/frontend/pp/05_ifdef.expect b/tests/frontend/pp/05_ifdef.expect new file mode 100644 index 00000000..c4869c45 --- /dev/null +++ b/tests/frontend/pp/05_ifdef.expect @@ -0,0 +1 @@ +int enabled = 1; diff --git a/tests/frontend/pp/empty_macro.c b/tests/frontend/pp/empty_macro.c new file mode 100644 index 00000000..13318671 --- /dev/null +++ b/tests/frontend/pp/empty_macro.c @@ -0,0 +1,2 @@ +#define EMPTY +int x EMPTY = 1; diff --git a/tests/frontend/pp/empty_macro.expect b/tests/frontend/pp/empty_macro.expect new file mode 100644 index 00000000..46481df0 --- /dev/null +++ b/tests/frontend/pp/empty_macro.expect @@ -0,0 +1 @@ +int x = 1; diff --git a/tests/frontend/pp/include_guard.c b/tests/frontend/pp/include_guard.c new file mode 100644 index 00000000..d13753b5 --- /dev/null +++ b/tests/frontend/pp/include_guard.c @@ -0,0 +1,4 @@ +#ifndef GUARD_H +#define GUARD_H +int guarded; +#endif diff --git a/tests/frontend/pp/include_guard.expect b/tests/frontend/pp/include_guard.expect new file mode 100644 index 00000000..f60a294a --- /dev/null +++ b/tests/frontend/pp/include_guard.expect @@ -0,0 +1 @@ +int guarded; diff --git a/tests/frontend/pp/line_continuation.c b/tests/frontend/pp/line_continuation.c new file mode 100644 index 00000000..d715914b --- /dev/null +++ b/tests/frontend/pp/line_continuation.c @@ -0,0 +1,3 @@ +#define LONG \ + 123 +int x = LONG; diff --git a/tests/frontend/pp/line_continuation.expect b/tests/frontend/pp/line_continuation.expect new file mode 100644 index 00000000..0d0efa38 --- /dev/null +++ b/tests/frontend/pp/line_continuation.expect @@ -0,0 +1 @@ +int x = 123; diff --git a/tests/frontend/pp/macro_indirection.c b/tests/frontend/pp/macro_indirection.c new file mode 100644 index 00000000..1b53a6f1 --- /dev/null +++ b/tests/frontend/pp/macro_indirection.c @@ -0,0 +1,3 @@ +#define A B +#define B 3 +int x = A; diff --git a/tests/frontend/pp/macro_indirection.expect b/tests/frontend/pp/macro_indirection.expect new file mode 100644 index 00000000..3694828b --- /dev/null +++ b/tests/frontend/pp/macro_indirection.expect @@ -0,0 +1 @@ +int x = 3; diff --git a/tests/frontend/pp/macro_undef.c b/tests/frontend/pp/macro_undef.c new file mode 100644 index 00000000..8865e629 --- /dev/null +++ b/tests/frontend/pp/macro_undef.c @@ -0,0 +1,4 @@ +#define FOO 1 +int a = FOO; +#undef FOO +int b = FOO; diff --git a/tests/frontend/pp/macro_undef.expect b/tests/frontend/pp/macro_undef.expect new file mode 100644 index 00000000..3aa14e59 --- /dev/null +++ b/tests/frontend/pp/macro_undef.expect @@ -0,0 +1,2 @@ +int a = 1; +int b = FOO; diff --git a/tests/frontend/pp/pragma_once.c b/tests/frontend/pp/pragma_once.c new file mode 100644 index 00000000..8a08415d --- /dev/null +++ b/tests/frontend/pp/pragma_once.c @@ -0,0 +1,2 @@ +#pragma once +int once; diff --git a/tests/frontend/pp/pragma_once.expect b/tests/frontend/pp/pragma_once.expect new file mode 100644 index 00000000..4c7ad461 --- /dev/null +++ b/tests/frontend/pp/pragma_once.expect @@ -0,0 +1 @@ +int once; diff --git a/tests/frontend/pp/predefined_macros.c b/tests/frontend/pp/predefined_macros.c new file mode 100644 index 00000000..e0e9f8f6 --- /dev/null +++ b/tests/frontend/pp/predefined_macros.c @@ -0,0 +1,3 @@ +int line = __LINE__; +const char *date = __DATE__; +const char *time = __TIME__; diff --git a/tests/frontend/pp/predefined_macros.expect b/tests/frontend/pp/predefined_macros.expect new file mode 100644 index 00000000..94b9d4f0 --- /dev/null +++ b/tests/frontend/pp/predefined_macros.expect @@ -0,0 +1,3 @@ +int line = 1; +const char *date = ""; +const char *time = "