From bb1444ab8e5bdb9f901ccd1190c99e25abaf19e0 Mon Sep 17 00:00:00 2001 From: Wonhyuk Yang Date: Fri, 19 Jun 2026 17:51:35 +0900 Subject: [PATCH 1/2] [Test] Add integer widening dtype-conversion regression test Guards the Spike VI_VV_EXT (vsext/vzext) lane bug where widening int conversions (int8/int16 -> wider via tensor.to) returned scrambled/zero output. Signed and uint8<128 only so it is independent of the separate uint8->int8 dtype issue (#238). Requires the riscv-isa-sim fix (PSAL-POSTECH/riscv-isa-sim#4) in the pinned Spike; add to the CI allowlist + bump thirdparty/github-releases.json spike tag once that release is cut. Co-Authored-By: Claude Opus 4.8 --- tests/ops/misc/test_widen_dtype.py | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 tests/ops/misc/test_widen_dtype.py diff --git a/tests/ops/misc/test_widen_dtype.py b/tests/ops/misc/test_widen_dtype.py new file mode 100644 index 00000000..9bc11099 --- /dev/null +++ b/tests/ops/misc/test_widen_dtype.py @@ -0,0 +1,30 @@ +import os +import sys +import torch +sys.path.insert(0, os.path.join(os.environ.get("TORCHSIM_DIR", default="/workspace/PyTorchSim"), "tests")) +from _pytorchsim_utils import test_result + + +def _widen(device, name, src_dtype, dst_dtype, lo, hi): + # Widening conversions lower to vsext.vf*/vzext.vf* (VI_VV_EXT). A Spike bug + # wrote every lane's result to lane 1 (vu_idx dropped), zeroing the rest; this + # guards against that regression. Signed / uint8<128 only, so the sign-extension + # is correct independent of the separate uint8->int8 dtype issue (#238). + a = torch.randint(lo, hi, (128, 128), dtype=src_dtype) + fn = lambda a: a.to(dst_dtype) + res = torch.compile(dynamic=False)(fn)(a.to(device=device)) + out = fn(a) + test_result(name, res, out) + + +def test_widen(device): + _widen(device, "int8->int16", torch.int8, torch.int16, -128, 128) + _widen(device, "int8->int32", torch.int8, torch.int32, -128, 128) + _widen(device, "int16->int32", torch.int16, torch.int32, -1000, 1000) + _widen(device, "uint8->int32", torch.uint8, torch.int32, 0, 128) + _widen(device, "uint8->float32", torch.uint8, torch.float32, 0, 128) + + +if __name__ == "__main__": + device = torch.device("npu:0") + test_widen(device) From 74b66b9898b4dfa3357e79b888f19350907b94bb Mon Sep 17 00:00:00 2001 From: Wonhyuk Yang Date: Fri, 19 Jun 2026 19:33:40 +0900 Subject: [PATCH 2/2] [CI] Bump Spike pin to v1.0.2 and run test_widen_dtype v1.0.2 includes the riscv-isa-sim VI_VV_EXT fix (PSAL-POSTECH/riscv-isa-sim#4) so integer widening conversions no longer scramble. Bumping the pin changes the thirdparty base-image hash, so ensure-base rebuilds the base with the new Spike. Wire test_widen_dtype.py into the allowlist now that the fixed Spike is pinned. Co-Authored-By: Claude Opus 4.8 --- .github/workflows/pytorchsim_test.yml | 19 +++++++++++++++++++ thirdparty/github-releases.json | 2 +- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/.github/workflows/pytorchsim_test.yml b/.github/workflows/pytorchsim_test.yml index 54a2345b..33e279fe 100644 --- a/.github/workflows/pytorchsim_test.yml +++ b/.github/workflows/pytorchsim_test.yml @@ -191,6 +191,25 @@ jobs: -e vpu_spad_size_kb_per_lane="${{ inputs.spad_size }}" \ ${{ inputs.image_name }} python3 PyTorchSim/tests/ops/view/test_floormod_axis_split.py + test_widen_dtype: + name: Run test_widen_dtype.py + runs-on: ubuntu-latest + steps: + - name: Log in to GitHub Container Registry + uses: docker/login-action@v3 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Run test_widen_dtype.py + run: | + echo "Running test_widen_dtype.py" + docker run --rm \ + -e vpu_num_lanes="${{ inputs.vector_lane }}" \ + -e vpu_spad_size_kb_per_lane="${{ inputs.spad_size }}" \ + ${{ inputs.image_name }} python3 PyTorchSim/tests/ops/misc/test_widen_dtype.py + test_matmul: name: Run test_matmul.py runs-on: ubuntu-latest diff --git a/thirdparty/github-releases.json b/thirdparty/github-releases.json index b641fd9a..4af6ccbd 100644 --- a/thirdparty/github-releases.json +++ b/thirdparty/github-releases.json @@ -13,7 +13,7 @@ }, "spike": { "repository": "PSAL-POSTECH/riscv-isa-sim", - "release_tag": "v1.0.1", + "release_tag": "v1.0.2", "asset_name": "spike-release.tar.gz" } }